Hello, I'm new to VHDL. I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%, 30%, and 50%? Thank you.
You should reformat your code. You cannot read which "else" belongs to which "if". I don't kniwnif its even possible to add 1 to a std_logic_vector. What you need, are 2 values. One for counting up and one for down. Typically you set a flag if you are counting up or not.
Chris wrote: > What you need, are 2 values. One for counting up and one for down. Indeed 2 values are needed. But only 1 for a counter, and the second for a compare value to toggle the output. Then its stupidly easy:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity PWM500Hz is port( clock : in STD_LOGIC; -- 50 Mhz pwmout : out STD_LOGIC); end PWM500Hz ; architecture Behavioral of PWM500Hz is signal cnt: integer range 0 to (50000000/500)-1 := 0; constant cmp: integer := (50000000/5000); -- PWM = 10% begin process(clock) begin if rising_edge(clock) then if cnt<(50000000/500)-1 then cnt<=cnt+1; else cnt<=0; end if; end if; end process; pwmout <= '1' when cnt<cmp else '0'; end Behavioral;