query related to verilog code

Thahseen Guest #4564222
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1
module encoder(clk,rst,en,en1,data,decoded_data);

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    input clk,rst,en,en1;

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    input [7:0]data;

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    output [7:0]decoded_data;

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    wire [7:0]btg;

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    reg [7:0]dec;

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    reg [5:0] mem[0:255];   // ENCODED

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    reg [5:0] mem1[0:255];  // DECODED

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    reg [7:0] mem2[0:255];  // OUTPUT

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    reg [7:0] mem3[0:255];  // BTG DATAS

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    reg [7:0]count,count1,count2;

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    integer fd;

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 always @(!rst) begin

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        mem[0]=6'b000000;  

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        mem1[0]=6'b000000;

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        mem2[0]=8'b00000000;

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        mem3[0]=8'b00000000;

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        count=8'b00000000;

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        count1=8'b00000000;

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        count2=8'b00000000;

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        dec=8'b00000000;

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    end

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    //pseudo_random p1(clk,rst,data);

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    binary_gray b1(data,btg);

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    always @(data) begin

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        fd=$fopen("outfile.txt");

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        $fdisplay(fd,"%b",data);

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    end

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    always @(btg) begin

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        if (btg[4] && btg[5] && en == 1) begin

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            count=count+1;

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            mem3[count]=btg;

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            mem[count]=~({btg[7],btg[6],btg[3],btg[2],btg[1],btg[0]} ^ mem[count-1]);

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            fd=$fopen("outfile1.txt");

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            $fdisplay(fd,"%b",mem[count]);

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        end else if (en == 1) begin

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            count=count+1;

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            mem3[count]=btg;

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            mem[count]=({btg[7],btg[6],btg[3],btg[2],btg[1],btg[0]} ^ mem[count-1]);

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            fd=$fopen("outfile1.txt");

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            $fdisplay(fd,"%b",mem[count]);

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        end

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    end

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    always @(btg) begin

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        if ((btg[4] && btg[5]) && en1 == 0) begin

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            count1=count1+1;

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            mem1[count1]=~((mem[count-1]) ^ (mem[count]));

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            dec={mem1[count1][5],mem1[count1][4],btg[5],btg[4],mem1[count1][3],mem1[count1][2],mem1[count1][1],mem1[count1][0]};

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            fd=$fopen("outfile2.txt");

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            $fdisplay(fd,"%b",mem1[count1]);

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        end else if (en1 == 0) begin

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            count1=count1+1;

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            mem1[count1]=((mem[count-1]) ^ (mem[count]));

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            dec={mem1[count1][5],mem1[count1][4],btg[5],btg[4],mem1[count1][3],mem1[count1][2],mem1[count1][1],mem1[count1][0]};

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            fd=$fopen("outfile2.txt");

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            $fdisplay(fd,"%b",mem1[count1]);

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        end

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    end

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    gray_binary g1(dec,decoded_data);

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    always @(btg) begin

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        count2=count2+1;

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        mem2[count2]=decoded_data;

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        fd=$fopen("outfile3.txt");

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        $fdisplay(fd,"%b",mem2[count2]);

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    end

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endmodule

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module binary_gray(a,b);

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    input [7:0]a;

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    output [7:0]b;

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    wire [7:0]b;

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    assign b={a[7],a[7]^a[6],a[6]^a[5],a[5]^a[4],a[4]^a[3],a[3]^a[2],a[2]^a[1],a[1]^a[0]};

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endmodule

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module gray_binary(a,b);

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    input [7:0]a;

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    output [7:0]b;

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    wire [7:0]b;

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    assign b={a[7],a[7]^a[6],b[6]^a[5],b[5]^a[4],b[4]^a[3],b[3]^a[2],b[2]^a[1],b[1]^a[0]};

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endmodule

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module pseudo_random(clk,rst,s);

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input clk,rst;

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output [8:1]s;

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reg [8:1]s;

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wire s0;

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// MODULO 2 ADDITION

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assign s0 = s[2] ^ s[3] ^ s[4] ^ s[8];

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// STATE MACHINE

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always @ (posedge clk or rst) begin

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// INITIAL STATE SHOULDN'T BE 000 => 100

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if(!rst) begin

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s[1] <= 0;

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s[2] <= 0;

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s[3] <= 0;

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s[4] <= 0;

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s[5] <= 0;

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s[6] <= 0;

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s[7] <= 0;

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s[8] <= 1;

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end else begin

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s[1] <= s[2];

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s[2] <= s[3];

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s[3] <= s[4];

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s[4] <= s[5];

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s[5] <= s[6];

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s[6] <= s[7];

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s[7] <= s[8];

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s[8] <= s0;

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end

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end

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endmodule



line 15: Unexpected event in always block sensitivity list.
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Lothar M. Moderator (Company: Titel) #4564255
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I don't know Verilog too much, but counters without a clock form 
combinatorial loops:
1
    ...

2
    always @(btg) begin

3
        if (btg[4] && btg[5] && en == 1) begin

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            count=count+1;

5
    ...

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    always @(btg) begin

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        count2=count2+1;

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    ...

And so forth.
Additionally to me it looks like some of those lists are incomplete:
In the qouted blocks above count and count2 are missing.

For the error message:
Try your code without the '!'.
A sensitivity list tells only to look for changes on the signals in 
it. So a negation sign is absolutely useless there. Think about that...


BTW: pls use [pre], [code] or [c] tags around your code.
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Lattice User Guest #4565364
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>
> For the error message:
> Try your code without the '!'.
> A sensitivity list tells only to look for changes on the signals in
> it. So a negation sign is absolutely useless there. Think about that...
>
Verilog allows expressions in the sensitivity list, but as with many 
constructs the synthesizer does not. However Lothar is right the ! does 
not do anything, a negated change is still a change.

Another problem with the code, is that the synthesizer does not allow 
assignments to a signal from multiple always blocks. Also legal in 
Verilog but not part of synthesizable subset.

I strongly suggest reading the coding style guide of the tool chain!
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