I don't know Verilog too much, but counters without a clock form
And so forth.
Additionally to me it looks like some of those lists are incomplete:
In the qouted blocks above count and count2 are missing.
For the error message:
Try your code without the '!'.
A sensitivity list tells only to look for changes on the signals in
it. So a negation sign is absolutely useless there. Think about that...
BTW: pls use [pre], [code] or [c] tags around your code.
>> For the error message:> Try your code without the '!'.> A sensitivity list tells only to look for changes on the signals in> it. So a negation sign is absolutely useless there. Think about that...>
Verilog allows expressions in the sensitivity list, but as with many
constructs the synthesizer does not. However Lothar is right the ! does
not do anything, a negated change is still a change.
Another problem with the code, is that the synthesizer does not allow
assignments to a signal from multiple always blocks. Also legal in
Verilog but not part of synthesizable subset.
I strongly suggest reading the coding style guide of the tool chain!