Help me please to write te vhdl code about the next delivery:
Consider the circuit in FigureA. It is a 4-bit synchronous counter,
which uses four T-type flip-flops. The counter increments the count
signal on each positive edge of the clock if the Enable signal is
asserted. The counter is reset to 0 by using the Reset signal. You need
to implement a 16-bit synchronous counter and alfter that you must
augment a vhdl file to use the pushbutton KEY0 as the Clock input,
switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays
HEX3-0 to display the hexadecimal count as your circuit operates.
Can i use 16t.flip_flop and Q(0)Q(1)Q(2)Q(3) for HEX0
Q(4)Q(5)Q(6)Q(7)Q(8) for HEX1
Q(9),Q(10),Q(11),Q(12) for HEX2
Q(13),Q(14),Q(15),Q(16) for HEX3 ?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Counter IS
PORT (Enable, Clock, Clear: IN STD_LOGIC;
Q: STD_LOGIC_VECTOR(15 downto 0));
END Counter;
ARCHITECTURE Behavior OF Counter IS
SIGNAL count: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
Q<= COUNT;
PROCESS(Clock,Clear)
BEGIN
IF Clear='1' THEN
count <= '000000000000000';
ELSIF Clock'EVENT AND Clock='1' THEN
???
-- I can't use Q <= Q+1;
END if
end process
end behavior;
Gustl B. wrote:> Hello, you just have to describe a T-FF and then connect them as a> chain.> So ... i did the firt 8 bits of the work, now do the remaining half :-)
Thanks,you re really kind. Your vhdl is really helpful!
Can you help me with the second part also, please?
augment a vhdl file to use the pushbutton KEY0 as the Clock input,
switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays
HEX3-0 to display the hexadecimal count as your circuit operates.
Hi!
to implement this, you need to write a constraint file! For this you
need the datasheet of your development board!
Additionally you need to write a a module to show each hex value on one
of the 7 segment digits!
this is ver easy with a case statement.
http://www.ics.uci.edu/~jmoorkan/vhdlref/cases.html
Why cant you use Q <= Q+1; ?
it would be way easier to do this this way and just care for the
overflow:
(ill do it for 8 bit)
signal counter : std_logic_vector (7 downto 0);
process(clk)
begin
if(rising_edge(clk)) then
if(counter="11111111) then
counter <= "00000000);
end if;
else
counter <= counter+1;
end if;
end process;
You can then just take the hex values: (for 16 bit counter)
signal hex3,hex2,hex1,hex0 : std_logic_vector (3 downto 0);
hex3 <= counter (15 downto 12);
hex2 <= counter (11 downto 8);
hex1 <= counter (7 downto 14);
hex0 <= counter (3 downto 0);
and map each to one 7_segment_decoder.
In your constraint file (.ucf) you just map your pins to the according
vhdl signals. If you need further help with this you need to provide
information what board you use!
if you use a button for clk input you should debounce it!
Ber 2. wrote:> -- I can't use Q <= Q+1;
What error messages do you get here?
> -- I can't use Q <= Q+1;
This is due to 2 major problems:
1. You must use an arithmetic package for calculations!
2. You cannot read outputs, but for the 'Q+1' you need to do this. Do
you remember: you have a local counter signal named count for
counting?
Take the numeric_std and use an integer for counting:
1
LIBRARYieee;
2
USEieee.std_logic_1164.all;
3
USEieee.numeric_std.all;
4
5
ENTITYCounterIS
6
PORT(Enable,Clock,Clear:INSTD_LOGIC;
7
Q:STD_LOGIC_VECTOR(15downto0));
8
ENDCounter;
9
10
ARCHITECTUREBehaviorOFCounterIS
11
SIGNALcount:integerrange0to65535:=0;
12
BEGIN
13
Q<=std_logic_vector(to_unsigned(COUNT,16));
14
15
PROCESS(Clock,Clear)BEGIN
16
IFClear='1'THEN
17
count<=0;
18
ELSIFrising_edge(Clock)THEN
19
ifcount<65535then
20
count<=count+1;
21
else-- wrap around
22
count<=0;
23
endif;
24
ENDif
25
endprocess
26
endbehavior;
alexxk wrote:> to implement this, you need to write a constraint file!
At least you must tell the toolchain what PINs you want to use and what
CLOCK frequency you have...
-gb- wrote:> I think in this homework he should actually describe the single FF. And> perhaps use it as a component.
That would be one of those stupid exercises leading to that extremely
chatty and unreadable "academic university VHDL".