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Help me please to write te vhdl code about the next delivery:
Consider the circuit in FigureA. It is a 4-bit synchronous counter,
which uses four T-type flip-flops. The counter increments the count
signal on each positive edge of the clock if the Enable signal is
asserted. The counter is reset to 0 by using the Reset signal. You need
to implement a 16-bit synchronous counter and alfter that you must
augment a vhdl file to use the pushbutton KEY0 as the Clock input,
switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays
HEX3-0 to display the hexadecimal count as your circuit operates.
Can i use 16t.flip_flop and Q(0)Q(1)Q(2)Q(3) for HEX0
Q(4)Q(5)Q(6)Q(7)Q(8) for HEX1
Q(9),Q(10),Q(11),Q(12) for HEX2
Q(13),Q(14),Q(15),Q(16) for HEX3 ?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Counter IS
PORT (Enable, Clock, Clear: IN STD_LOGIC;
Q: STD_LOGIC_VECTOR(15 downto 0));
END Counter;
ARCHITECTURE Behavior OF Counter IS
SIGNAL count: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
Q<= COUNT;
PROCESS(Clock,Clear)
BEGIN
IF Clear='1' THEN
count <= '000000000000000';
ELSIF Clock'EVENT AND Clock='1' THEN
???
-- I can't use Q <= Q+1;
END if
end process
end behavior;
Hello, you just have to describe a T-FF and then connect them as a chain. The description of the counter (just 8 bits):
library ieee; use ieee.std_logic_1164.all; entity counter_16bit is Port( clock: in STD_LOGIC; enable: in STD_LOGIC; reset: in STD_LOGIC; Q: out STD_LOGIC_VECTOR(7 downto 0)); end counter_16bit; architecture behavior of counter_16bit is signal BIT_0, BIT_1, BIT_2, BIT_3, BIT_4, BIT_5, BIT_6, BIT_7: std_logic:= '0'; begin Q <= BIT_7 & BIT_6 & BIT_5 & BIT_4 & BIT_3 & BIT_2 & BIT_1 & BIT_0; --FF_0: process (clock, enable, reset) begin if reset = '1' then BIT_0 <= '0'; elsif rising_edge(clock) AND enable = '1' then BIT_0 <= NOT BIT_0; end if; end process; --FF_1: process (clock, enable, reset) begin if reset = '1' then BIT_1 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_0 = '1' then BIT_1 <= NOT BIT_1; end if; end process; --FF_2: process (clock, enable, reset) begin if reset = '1' then BIT_2 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_1 = '1' then BIT_2 <= NOT BIT_2; end if; end process; --FF_3: process (clock, enable, reset) begin if reset = '1' then BIT_3 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_2 = '1' then BIT_3 <= NOT BIT_3; end if; end process; --FF_4: process (clock, enable, reset) begin if reset = '1' then BIT_4 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_3 = '1' then BIT_4 <= NOT BIT_4; end if; end process; --FF_5: process (clock, enable, reset) begin if reset = '1' then BIT_5 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_4 = '1' then BIT_5 <= NOT BIT_5; end if; end process; --FF_6: process (clock, enable, reset) begin if reset = '1' then BIT_6 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_5 = '1' then BIT_6 <= NOT BIT_6; end if; end process; --FF_7: process (clock, enable, reset) begin if reset = '1' then BIT_7 <= '0'; elsif rising_edge(clock) AND enable = '1' AND BIT_6 = '1' then BIT_7 <= NOT BIT_7; end if; end process; end behavior; |
And here the testbench:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; use IEEE.numeric_std.all; ENTITY counter_16bit_bench IS END counter_16bit_bench; ARCHITECTURE behavior OF counter_16bit_bench IS COMPONENT counter_16bit is Port( clock: in STD_LOGIC; enable: in STD_LOGIC; reset: in STD_LOGIC; Q: out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; signal clock, enable, reset : std_logic := '0'; signal Q : std_logic_vector(7 downto 0); constant clk_half_period : time := 5 ns; signal clk: std_logic:='0'; signal state: integer range 0 to 2:=0; signal counter: integer range 0 to 63:=0; BEGIN uut: counter_16bit PORT MAP ( clock => clock, enable => enable, reset => reset, Q => Q ); clk <= not clk after clk_half_period; process begin wait until rising_edge(clk); if state = 0 then counter <= counter +1; enable <= '1'; clock <= to_unsigned(counter,6)(0); if counter = 43 then state <= state +1; counter <= 0; reset <= '1'; end if; elsif state = 1 then reset <= '0'; counter <= counter +1; clock <= to_unsigned(counter,6)(0); if counter = 13 then enable <= '0'; end if; if counter = 27 then state <= state +1; enable <= '1'; end if; elsif state = 2 then counter <= counter +1; clock <= to_unsigned(counter,6)(0); end if; end process; END; |
So ... i did the firt 8 bits of the work, now do the remaining half :-)
Gustl B. wrote: > Hello, you just have to describe a T-FF and then connect them as a > chain. > So ... i did the firt 8 bits of the work, now do the remaining half :-) Thanks,you re really kind. Your vhdl is really helpful! Can you help me with the second part also, please? augment a vhdl file to use the pushbutton KEY0 as the Clock input, switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays HEX3-0 to display the hexadecimal count as your circuit operates.
Hi! to implement this, you need to write a constraint file! For this you need the datasheet of your development board! Additionally you need to write a a module to show each hex value on one of the 7 segment digits! this is ver easy with a case statement. http://www.ics.uci.edu/~jmoorkan/vhdlref/cases.html Why cant you use Q <= Q+1; ? it would be way easier to do this this way and just care for the overflow: (ill do it for 8 bit) signal counter : std_logic_vector (7 downto 0); process(clk) begin if(rising_edge(clk)) then if(counter="11111111) then counter <= "00000000); end if; else counter <= counter+1; end if; end process; You can then just take the hex values: (for 16 bit counter) signal hex3,hex2,hex1,hex0 : std_logic_vector (3 downto 0); hex3 <= counter (15 downto 12); hex2 <= counter (11 downto 8); hex1 <= counter (7 downto 14); hex0 <= counter (3 downto 0); and map each to one 7_segment_decoder. In your constraint file (.ucf) you just map your pins to the according vhdl signals. If you need further help with this you need to provide information what board you use! if you use a button for clk input you should debounce it!
Ber 2. wrote: > -- I can't use Q <= Q+1; What error messages do you get here? > -- I can't use Q <= Q+1; This is due to 2 major problems: 1. You must use an arithmetic package for calculations! 2. You cannot read outputs, but for the 'Q+1' you need to do this. Do you remember: you have a local counter signal named count for counting? Take the numeric_std and use an integer for counting:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY Counter IS PORT (Enable, Clock, Clear: IN STD_LOGIC; Q: STD_LOGIC_VECTOR(15 downto 0)); END Counter; ARCHITECTURE Behavior OF Counter IS SIGNAL count: integer range 0 to 65535 := 0; BEGIN Q <= std_logic_vector(to_unsigned(COUNT,16)); PROCESS(Clock,Clear) BEGIN IF Clear='1' THEN count <= 0; ELSIF rising_edge(Clock) THEN if count<65535 then count <= count+1; else -- wrap around count <= 0; end if; END if end process end behavior; |
alexxk wrote: > to implement this, you need to write a constraint file! At least you must tell the toolchain what PINs you want to use and what CLOCK frequency you have...
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Edited by Moderator
I think in this homework he should actually describe the single FF. And perhaps use it as a component.
-gb- wrote: > I think in this homework he should actually describe the single FF. And > perhaps use it as a component. That would be one of those stupid exercises leading to that extremely chatty and unreadable "academic university VHDL".
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Edited by Moderator
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