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Forum: FPGA, VHDL & Verilog Synchronizing reset signal used as a combinational logic


von Robert (Guest)


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Hallo,

I want to synchronize this combinational logic used as a reset signal. I 
tried adding registers (flipflops) to remove the glitches. But it does 
not seem to work. Is there any other solution? (See attached image)

von Lothar M. (lkmiller) (Moderator)


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Robert wrote:
> But it does not seem to work.
How do you see that?
What do you expect and what do you get instead?

> Is there any other solution?
For what problem?

BTW: how many clocks are in your design? If its a number greater than 1, 
then we know what the problem is...

von Robert (Guest)


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Lothar M. wrote:
> Robert wrote:
>> But it does not seem to work.
> How do you see that?
> What do you expect and what do you get instead?
>
I get a Critical Warning : Combinational Logic Used as a Reset Signal 
Should be Synchronized


> BTW: how many clocks are in your design? If its a number greater than 1,
> then we know what the problem is...

PLL generates a 50MHz Clock which is the system clock. But there are few 
generated clocks. This module uses a 150MHz Clock

von Lothar M. (lkmiller) (Moderator)


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Robert wrote:
> I get a Critical Warning :
> Combinational Logic Used as a Reset Signal Should be Synchronized
The synthesizer is right.
Never ever use asynchronous combinatorial resets.
If you do that in a counter with e.g. 16 flipflops, then the next glitch 
in that combinatorial path will reset 3..12 (or any random number 
between 0 and 16) of those flipflops. That will be dependent on supply 
volatage and temperature and it will give you some surprising effects.

And even a FSM is only a little bit more complex counter...

> But there are few generated clocks.
A beginners design must have only 1 clock. All the rest is done by 
clock enable signals.
Read the last sentence of this school exercise:
https://embdev.net/topic/394849#4539869
Having only 1 clock will help you getting a reproduceable synchronous 
design.

: Edited by Moderator

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