Hallo, This division consumes a lot of logic elements which affects the timing. Since the denominator can vary according to the incoming value, I am not able to equate it to a 2**x value which reduces the logic elements.

timer_us := SYS_FREQ/(ctr_freq)-1; -- say (40000000/1000000 -1) |

Any suggestions?

How often/how fast need this division take place? Maybe you could switch to a state machine, which control a counter, a subtraction and a comparator... DUke

Vik wrote: > This division consumes a lot of logic elements which affects the timing. A pure combinatorial divisionisextremely demanding. So usually a division in hardware is done in several steps (like a division by hand on a sheet of paper: each digit is one step of calculation). Therefore such a division takes several clock cycles. Have a look there (try Google translator, its German): http://www.lothar-miller.de/s9y/archives/29-Division-in-VHDL.html

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