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Forum: FPGA, VHDL & Verilog Alternatiive to reduce the number of logic elements in divisionHallo, This division consumes a lot of logic elements which affects the timing. Since the denominator can vary according to the incoming value, I am not able to equate it to a 2**x value which reduces the logic elements.
Any suggestions? How often/how fast need this division take place? Maybe you could switch to a state machine, which control a counter, a subtraction and a comparator... DUke Vik wrote: > This division consumes a lot of logic elements which affects the timing. A pure combinatorial division is extremely demanding. So usually a division in hardware is done in several steps (like a division by hand on a sheet of paper: each digit is one step of calculation). Therefore such a division takes several clock cycles. Have a look there (try Google translator, its German): http://www.lothar-miller.de/s9y/archives/29-Division-in-VHDL.html :
Edited by Moderator
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