Alternatiive to reduce the number of logic elements in division

Vik Guest #4600974
Rate this post
• ▲ useful
▼ not useful 
Hallo,

This division consumes a lot of logic elements which affects the timing. 
Since the denominator can vary according to the incoming value, I am not 
able to equate it to a 2**x value which reduces the logic elements.

1
timer_us := SYS_FREQ/(ctr_freq)-1; -- say (40000000/1000000 -1)

Any suggestions?
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #4601439
Rate this post
• ▲ useful
▼ not useful 
Vik wrote:
> This division consumes a lot of logic elements which affects the timing.
A pure combinatorial division is extremely demanding.
So usually a division in hardware is done in several steps (like a 
division by hand on a sheet of paper: each digit is one step of 
calculation). Therefore such a division takes several clock cycles.
Have a look there (try Google translator, its German): 
http://www.lothar-miller.de/s9y/archives/29-Division-in-VHDL.html
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.