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Forum: FPGA, VHDL & Verilog VHDL: Port map with std_logic_vector


VHDL: Port map with std_logic_vector
von LiZhen L. (Guest)

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I'm trying to simulate a ring oscillator driving a 6-bit counter. The 
counter works fine. I've declared a new signal to store the output from 
the counter, but I'm not so sure about the port map for the counter when 
I included it as a part of the ring oscillator.

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--6 BIT COUNTER (works fine)

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LIBRARY IEEE;

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USE IEEE.STD_LOGIC_1164.ALL;

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USE IEEE.STD_LOGIC_ARITH.All;

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USE IEEE.STD_LOGIC_SIGNED.ALL;

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ENTITY counter_vhdl IS

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PORT (clock,reset     : IN std_logic;

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      output          : OUT std_logic_vector(0 TO 5));

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END counter_vhdl;

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ARCHITECTURE behav OF counter_vhdl IS 

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CONSTANT Tdelay  : time := 10 ns; -- Typical delay

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BEGIN

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check_clock : PROCESS(clock, reset)

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VARIABLE count  : std_logic_vector(0 TO 5) := "000000";

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BEGIN

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IF ( reset = '0') THEN

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  count := "000000";

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  ELSIF ( clock'event and clock = '1') THEN

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    IF (count = "111111") THEN

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      count := "000000";

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    ELSE

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      count :=  count + "000001";

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    END IF;

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END IF;

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  output <= count AFTER Tdelay;

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END PROCESS check_clock;

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END behav;

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--Ring oscillator with counter

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LIBRARY IEEE;

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USE IEEE.STD_LOGIC_1164.ALL;

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USE IEEE.STD_LOGIC_ARITH.All;

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USE IEEE.STD_LOGIC_SIGNED.ALL;

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ENTITY ring_vhdl IS

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PORT(  ring_osc_enb,reset   : IN std_logic;

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       OUT1, OUT2    : OUT std_logic; 

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       data_out      : OUT std_logic_vector(0 TO 5));

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END ring_vhdl;

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ARCHITECTURE struct OF ring_vhdl IS

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  COMPONENT OSCILLATOR

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    PORT (ENB: IN std_logic; OUT1, OUT2 : OUT std_logic);

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  END COMPONENT;

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  COMPONENT COUNTER 

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               PORT(clock,reset: IN std_logic;

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                    data_out   : OUT std_logic_vector(0 TO 5));

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        END COMPONENT;

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  signal osc1, osc2  : std_logic;

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  signal count6     : std_logic_vector(0 TO 5);  

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  FOR u1: OSCILLATOR USE ENTITY WORK.ring_oscillator_vhdl(struct);

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  FOR u2: COUNTER USE ENTITY WORK.counter_vhdl(behav);

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  BEGIN

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    u1:OSCILLATOR PORT MAP(ring_osc_enb,osc1,osc2);

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    u2:COUNTER PORT MAP(osc1,reset,count6);    <-----

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    OUT1 <= osc1;

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    OUT2 <= osc2;

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    data_out <= count6;

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END struct;


  


  



  

  
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    Re: VHDL: Port map with std_logic_vector
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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And what's the problem now?

LiZhen L. wrote:
> but I'm not so sure about the port map for the counter
Indeed: an ascending bit order is unusual for counters. In your counter 
bit 5 is the fastest toggling bit. In 99.9999% around the world always 
bit 0 is the lowest and fastest toggling bit.
In short words: I would declare a vector always with "downto". Billions 
of people expect it that way...

For the port map: do not use positional assignment. Better use explicit 
assignment:
1
   u2:COUNTER PORT MAP(clock=>osc1,reset=>reset,data_out=>count6);


BTW: did you find that about the [vhdl] formatting options tags?

  


  



  

  
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