From a first glance I would say, that the circuit isn't a JK-FF as it 
lacks feedbacks from the outputs to the input-and-gates of the 
complementary parts.

You omitted specification of the FF you want to create. What kind of 
JK-FF would you like to create? In other words: With which truth value 
table? Or let me express my question as: When do you want it change its 
state, and when not?

seems all hope is gone in the Moment q equals qn, the FF will never 
recover from this state. Try Initial values to resolves this invalid 
state.

Dan N. wrote:
> crystal bowl wrote:
>> seems all hope is gone in the Moment q equals qn, the FF will never
>> recover from this state. Try Initial values to resolves this invalid
>> state.
>
> Would you explaine more? I'm afraid I didn't catch what you extacly
> mean.

Presumed crystal's allowance I try to explain instead of him:

The state of Q = not Q = 0 isn't a legal stationary state. Q and not Q 
have to have different states in every case. (Despite very short moments 
where there are about to change).
Starting the simulation with Q = not Q = 0 caused a lock in that state. 
The internal signals i1 and i2 could never change to 1 (as the and would 
only go to 1 if all inputs are 1). So the state wont change whatever you 
do at clock or J or K.

My English is sort of strange today, sorry. :-) Should have re-read it 
before posting.


Presumed crystal's allowance I'll try to explain instead of him:

The state of Q = not Q = 0 isn't a valid stationary state. Q and not Q
have to have different states at every moment. (Despite very short 
moments
when they are about to change).

Starting the simulation with Q = not Q = 0 causes a lock in that state.
The internal signals i1 and i2 could never change to 1 (as the and-gate 
would only output a 1, if all inputs are 1). So the state wont change, 
whatever you do at clock or J or K inputs.

Hope, that's a little bit better.

Unfortunately I am a bit busy now, so let me give you some generic 
advice right now.

1. You still have undefined signals (as you may notice red lines in your 
simulation output).

2. Consider uninitialized signals (f.e. internal i1 and i2) and C,J,K in 
your testbench. Take care that these initializations are not 
contradictory as set i1 or i2 to an output value which could not occur 
at the very combination of the and-gates inputs.

3. I'm not used to your very simulation software. But in case of using 
feedbacks it's an important question if simulate real circuit or only 
the idealized circuit (there is a formal expression but I don't remember 
it right now). The former is done, if you do a "Post-Place-N-Route" 
simulation as there the real devices delay is considered.
The latter does not consider that, which is good for circuits which are 
only combinatorial (which do not contain feedbacks). If you 
intentionally want to do the latter, you have to provide an architecture 
which explicitly describes delays.

4. Point 3 is related also to your stimulus. Your edges, that of clk, j 
and k occur seemingly at the very same point in time. This leads likely 
to unexpected results - which in detail depend on the simulation 
software implementation. It would be, formally, better to change J or K 
before changing clk. Doing it at the same moment gives formally a 
contradictory or at least dubious condition for the gates.

5. I'm still convinced that the structure is not a JK-FF. I wrote this 
in my first post and described the deviation from the form I remember. 
Please check that.

I hope that helps you further.
If anybody else sees any error in my post, please feel free to correct 
it.

Good luck.