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Forum: FPGA, VHDL & Verilog Machx02 User Flash Memory


von Chris C. (customchris)


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Hi guys, I just can't seem to wrap my head around this one, I would like 
to implement the user flash into my project to use like eeprom, I'm 
hoping someone has a very basic example, like std_logic_vector of 15 
down to 0 "input" and the same for "output", upon button press input is 
locked in memory for use on power up at "output".

I've read the app notes from Lattice, I just can't visualize how to 
create this, would be fantastic if there was a simple example, just like 
a blink sketch or hello world.

Thank you guys.

von Chris C. (customchris)


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Looks like I might just have a better chance at interfacing NVSram or 
spi flash/eeprom. Not enough examples to help me understand how to use 
this feature, I can't even figure out how to use the softcores out 
there.

von Holger (Guest)


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Hello here is hint for you how to use IPexpress
http://datasheet.octopart.com/LCMXO2-4000HC-4TG144I-Lattice-Semiconductor-datasheet-17019214.pdf
EFB Module in IPexpress
Page 138.
I send you later more info how to bind the ipexpress module *.ipx in 
your project
und compile it with a simple RTL modules.

Greetings Holger.

von Holger (Guest)


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Holger wrote:
> I send you later more info how to bind the ipexpress module *.ipx in
> your project
Task 2: Create an IPexpress Module at Page 16-<....

Click Import IPX to Diamond project.



Link:
https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwjC4tGZ1afMAhXLkSwKHa9BBpIQFggcMAA&url=http%3A%2F%2Fwww.latticesemi.com%2F~%2Fmedia%2FLatticeSemi%2FDocuments%2FTutorials%2FLZ%2FLatticeDiamondTutorial37.pdf%3Fdocument_id%3D51563&usg=AFQjCNF45OYAS-sYGErWZb0ol-LxbZtYFg

This is for a siple pll module via IPexpress,(binding in a project)
 but you see more resources for your Hardended Machxo2 Chip. EFB.
SPI I2C TIMER ect.pp.


Geetings Holger.

von Chris C. (customchris)


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This looks promising, thank you, every bit helps.

von Chris C. (customchris)


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Yeah none of this is making any sense, its not clear enough on how to 
generate the Ipexpress efb and whatever is needed to get UFM, every 
document is very vague about what to do, and just about every paragraph 
tells you to look into a different pdf to learn something else, it all 
seems to be a vicious circle of info for those who already know how to 
interact with the ise and import files/work the ports, Im coming from 
arduino environment where there are very well written and explained 
examples, I've somehow been able to get my project very well where it 
needs to be and it performs fantastically, in the beginning i taught 
myself how to add a very crude spi function to read a device with timers 
feeding timers that ran a When case, in the when case i controlled the 
Chip select, Mosi, Miso, and the Serial clock, with the help of a nifty 
logic analyzer i was able to see these lines and adjust to mimic what 
was shown in the datasheet for a spi transaction. the only thing im 
missing is a single on the fly adjustable  16bit memory location.

von Chris C. (customchris)


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I'm to the point where im willing to hire someone to help me out, if my 
boss and i cant figure this out tomorrow, this is vital to finishing my 
project, and i really would like to learn this, seems be a huge lack in 
lattice fpga tutorials and examples, xilinx is so plentiful in examples 
but none of which that i have found are in the Non Volatile platforms 
with internal flash.

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