1 | LIBRARY IEEE;
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2 | USE IEEE.numeric_std.all;
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3 | USE IEEE.std_logic_1164.all;
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4 |
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5 | ENTITY i_Soll_Skal IS
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6 |
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7 | GENERIC(
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8 | ADC_Res : INTEGER:= 4095;
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9 | ADC_Res_I : INTEGER:= 9840;
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10 |
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11 |
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12 | );
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13 |
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14 | PORT(
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15 | sys_clk,reset : IN STD_LOGIC;
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16 | i_Sample_Clock : IN STD_LOGIC;
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17 | i_sollwert : IN STD_LOGIC_VECTOR(13 downto 0); -- Input Sollwert
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18 | i_istwert : IN STD_LOGIC_VECTOR(11 downto 0); -- Input Istwert (IFact)
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19 | o_sollwert : OUT STD_LOGIC_VECTOR(15 downto 0); -- Scaled Sollwert
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20 | o_istwert : OUT STD_LOGIC_VECTOR(15 downto 0); -- Scaled Istwert
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21 | o_new_data : OUT STD_LOGIC; -- Trigger to PID for new data
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22 |
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23 | );
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24 |
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25 | END ENTITY i_Soll_Skal;
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26 |
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27 | ARCHITECTURE behaviour OF i_Soll_Skal IS
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28 |
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29 | --Altera-Divider
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30 | --Typ: lpm_divide, 24/12 Bit (unsigned)
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31 | COMPONENT lpm_divide_44_24_pip
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32 | PORT
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33 | (
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34 | clock : IN STD_LOGIC ;
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35 | denom : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
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36 | numer : IN STD_LOGIC_VECTOR (43 DOWNTO 0);
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37 | quotient : OUT STD_LOGIC_VECTOR (43 DOWNTO 0)
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38 | );
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39 | END COMPONENT;
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40 |
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41 |
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42 | -- Signals
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43 | signal s_Div_N : STD_LOGIC_VECTOR(43 DOWNTO 0);
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44 | signal s_Div_D : STD_LOGIC_VECTOR(23 DOWNTO 0);
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45 | signal s_Div_Q : STD_LOGIC_VECTOR(43 DOWNTO 0);
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46 | signal s_clk : STD_LOGIC;
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47 |
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48 | BEGIN
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49 |
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50 | div : lpm_divide_44_24_pip
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51 | PORT MAP
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52 | (
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53 | clock => s_clk,
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54 | denom => s_Div_D,
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55 | numer => s_Div_N,
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56 | quotient => s_Div_Q
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57 | );
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58 |
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59 | calc_wert : PROCESS(reset, sys_clk)
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60 | variable v_Sample_Clock : std_logic;
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61 | variable v_sollwert : unsigned(13 downto 0);
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62 | variable v_actVal : std_logic_vector(11 downto 0);
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63 | variable v_numer : unsigned(43 downto 0);
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64 | variable v_denom : unsigned(23 downto 0);
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65 | variable v_startNewCalc : std_logic;
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66 | variable v_calc : unsigned(1 DOWNTO 0);
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67 | variable v_div_result : std_logic_vector(35 downto 0);
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68 | variable v_updateVal : std_logic;
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69 | variable v_clk : std_logic;
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70 | BEGIN
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71 |
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72 |
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73 | IF reset = '0' THEN
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74 | -- Asynchronous reset
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75 | v_Sample_Clock := '0';
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76 | v_actVal := (others => '0');
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77 | v_numer := (others => '0');
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78 | v_denom := (others => '0');
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79 | v_startNewCalc := '0';
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80 | v_calc := (others => '0');
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81 | v_div_result := (others => '0');
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82 | v_updateVal := '0';
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83 |
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84 | ELSIF rising_edge(sys_clk) THEN
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85 | -- Update Istwert/IFact
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86 | o_new_data <= '0';
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87 |
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88 |
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89 | IF i_Sample_Clock = '1' AND v_Sample_Clock = '0' THEN
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90 |
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91 | v_actVal := i_istwert;
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92 | v_numer := v_sollwert * (to_unsigned(ADC_Res,30));
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93 | v_denom := to_unsigned(ADC_Res_I,24);
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94 | v_startNewCalc := '1';
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95 | v_clk := sys_clk; -- '1';
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96 | END IF;
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97 | v_Sample_Clock := i_Sample_Clock;
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98 |
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99 | IF v_updateVal = '1' THEN
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100 | o_sollwert <= "0000" & v_div_result(11 downto 0);
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101 | o_istwert <= "0000" & v_actVal;
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102 | o_new_data <= '1';
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103 | v_updateVal := '0';
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104 | END IF;
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105 |
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106 |
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107 | CASE v_calc IS
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108 |
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109 | WHEN "01" => s_Div_D <= std_logic_vector(v_denom);
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110 | s_Div_N <= std_logic_vector(v_numer);
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111 | s_clk <= v_clk;
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112 | WHEN "10" => v_div_result := s_Div_Q(35 downto 0);
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113 | v_updateVal := '1';
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114 | v_calc := "00";
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115 | s_clk <= v_clk;
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116 | WHEN OTHERS => NULL;
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117 | END CASE;
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118 |
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119 | IF v_startNewCalc = '1' OR v_calc /= "00" THEN
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120 | v_calc := v_calc + 1;
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121 | END IF;
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122 |
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123 | v_startNewCalc := '0';
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124 | END IF;
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125 |
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126 | END PROCESS calc_wert;
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127 |
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128 | END ARCHITECTURE behaviour;
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