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Forum: FPGA, VHDL & Verilog Clock port and any other port of a register should not be driven by the same signal source


von Robert (Guest)


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Hallo,

I get this Warning from Altera Design Assistant for the below:

Clock port and any other port of a register should not be driven by the 
same signal source

Critical Warning (308012): Node 
"App_Logic:inst1|LGVCtrl:inst1|i_Soll_Skal:inst|s_clk"

I previously made some changes to this to meet Timing requirements. I 
tried driving just a '1' instead of driving the sys_clk to v_clk. But 
the timing requirements do not meet when I do so. Any suggestions?
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LIBRARY IEEE;
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USE IEEE.numeric_std.all;
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USE IEEE.std_logic_1164.all;
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ENTITY i_Soll_Skal IS
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GENERIC(
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    ADC_Res       : INTEGER:=  4095; 
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    ADC_Res_I    : INTEGER:= 9840;       
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);
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PORT(
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    sys_clk,reset   : IN STD_LOGIC;
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    i_Sample_Clock  : IN STD_LOGIC;
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    i_sollwert     : IN STD_LOGIC_VECTOR(13 downto 0);   -- Input Sollwert
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    i_istwert    : IN STD_LOGIC_VECTOR(11 downto 0);    -- Input Istwert (IFact)    
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    o_sollwert    : OUT STD_LOGIC_VECTOR(15 downto 0);   -- Scaled Sollwert 
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    o_istwert    : OUT STD_LOGIC_VECTOR(15 downto 0);   -- Scaled Istwert 
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    o_new_data     : OUT STD_LOGIC;                       -- Trigger to PID for new data
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);
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END ENTITY i_Soll_Skal;
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ARCHITECTURE behaviour OF i_Soll_Skal IS
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--Altera-Divider 
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  --Typ: lpm_divide, 24/12 Bit (unsigned)
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  COMPONENT lpm_divide_44_24_pip
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    PORT
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    (
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    clock    : IN STD_LOGIC ;
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    denom    : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
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    numer    : IN STD_LOGIC_VECTOR (43 DOWNTO 0);
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    quotient  : OUT STD_LOGIC_VECTOR (43 DOWNTO 0)
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    );
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  END COMPONENT;
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  -- Signals  
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  signal s_Div_N      : STD_LOGIC_VECTOR(43 DOWNTO 0);
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  signal s_Div_D      : STD_LOGIC_VECTOR(23 DOWNTO 0);
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  signal s_Div_Q      : STD_LOGIC_VECTOR(43 DOWNTO 0);
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  signal s_clk      : STD_LOGIC;
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BEGIN
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div : lpm_divide_44_24_pip
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  PORT MAP
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  (
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     clock    => s_clk,
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    denom    => s_Div_D,
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    numer    => s_Div_N,
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    quotient  => s_Div_Q
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  );
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calc_wert : PROCESS(reset, sys_clk)
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  variable v_Sample_Clock      : std_logic;
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  variable v_sollwert        : unsigned(13 downto 0);
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  variable v_actVal          : std_logic_vector(11 downto 0);
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  variable v_numer          : unsigned(43 downto 0);
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  variable v_denom          : unsigned(23 downto 0);
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  variable v_startNewCalc      : std_logic;
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  variable v_calc    : unsigned(1 DOWNTO 0);
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  variable v_div_result      : std_logic_vector(35 downto 0);
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  variable v_updateVal        : std_logic;
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  variable v_clk                : std_logic;
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BEGIN
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  IF reset = '0' THEN
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    -- Asynchronous reset
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    v_Sample_Clock      := '0';
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    v_actVal          := (others => '0');
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    v_numer          := (others => '0');
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    v_denom          := (others => '0');
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    v_startNewCalc      := '0';
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    v_calc    := (others => '0');
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    v_div_result      := (others => '0');
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    v_updateVal        := '0';
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  ELSIF rising_edge(sys_clk) THEN    
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    -- Update Istwert/IFact
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    o_new_data      <= '0';
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    IF i_Sample_Clock = '1' AND v_Sample_Clock = '0' THEN
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        v_actVal        := i_istwert; 
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        v_numer         := v_sollwert * (to_unsigned(ADC_Res,30));
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        v_denom         := to_unsigned(ADC_Res_I,24);
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        v_startNewCalc    := '1';
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          v_clk             := sys_clk; -- '1';
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    END IF;
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    v_Sample_Clock  := i_Sample_Clock;
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    IF v_updateVal = '1' THEN
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      o_sollwert  <= "0000" & v_div_result(11 downto 0); 
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      o_istwert  <= "0000" & v_actVal;            
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      o_new_data  <= '1';                           
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      v_updateVal  := '0';
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    END IF;
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    CASE v_calc IS 
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       WHEN "01" =>  s_Div_D        <= std_logic_vector(v_denom);
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                s_Div_N        <= std_logic_vector(v_numer);
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                  s_clk             <= v_clk;    
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      WHEN "10" =>  v_div_result    := s_Div_Q(35 downto 0);
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                v_updateVal      := '1';
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                v_calc  := "00";
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                s_clk             <= v_clk;  
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      WHEN OTHERS => NULL;
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    END CASE;
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    IF v_startNewCalc = '1' OR v_calc /= "00" THEN
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      v_calc  := v_calc + 1;
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    END IF;
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    v_startNewCalc  := '0';  
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  END IF;
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END PROCESS calc_wert;
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END ARCHITECTURE behaviour;

von Achim S. (Guest)


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inside the FPGA a signal is either a standard logic signal or it is a 
clock. Compared to standard logic signals clocks run on own, separate 
CLK-lines in the FPGA and are driven by own, separate buffers. And 
clocks have a different function: they "trigger" a flip flop, while 
standard logic signals run through logic gates to deliver e.g. the 
data-input for the flip-flop.

Do not try, to derive clocks from logic signals - it won't work. If a 
signal should work as clock, it has to stem from a clock source (a 
clk-input or a PLL or ...), it must not stem from standard logic gates.

In your actual design you assign sys_clk to v_clk, then you assign v_clk 
to s_clk, and then you use s_clk to drive the clock-input of your 
divider. Skip the whole assignment chain: use sys_clk to drive the 
clock-input of your divider directly.

If your intention is, that the divider is only active in some cycles of 
sys_clk and is stall in other cycles of sys_clk, then redesign your 
divider so that it uses a Clock-Enable input and set it Clock Enable 
active only in the desired cycles of sys_clk.

von lcsdesigner (Guest)


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As said you are driving two destinations without a required clock Buffet

von Robert (Guest)


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Thank you. I altered the design directly assigning to the divider clock. 
It did not meet the timing requirements. But solved it finally.

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