uart fifo full

Anan H. OP (Company: ISO) #4583003
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hello.

from pang chu book

"""The full and empty status of the respective FIFO buffers can be
tested by consecutively receiving and transmitting more than four data 
words.
my question is it possible to increase the number of data word that fifo 
can contain"""


in the uart code the fifo just 4 data words like when u send from 
hypertermianl word "" hello""
the fpga board turn it back like this "hellh"

it is possible to increase it, to make the word " hello " when i send 
from hypertermianl to fpga .. the fpga turn it back to hyperwindow " 
hello" not hellh"?

if it possible how can i do it ? if it not, why??!

thanks alot ..
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Anan H. OP (Company: ISO) #4583288
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do u mean

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.NUMERIC_STD.ALL;

4


5
entity fifo is

6
  generic(

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    B: natural := 8;  -- Number of bits

8
    W: natural := 4    -- Number of address bits

9
  );

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  port(

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    clk, rst: in std_logic;

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    rd, wr: in std_logic;

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    w_data: in std_logic_vector(B-1 downto 0);

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    empty, full: out std_logic;

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    r_data: out std_logic_vector(B-1 downto 0)

16
  );


do u mean the w to change to 5? this is the number of adress bits in 
fifo ..

add it already the number of bits is 8
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René D. (Company: www.dossmatik.de) #4583671
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Anan H. wrote:
> do u mean
>
>
1
library IEEE;

2
> use IEEE.STD_LOGIC_1164.ALL;

3
> use IEEE.NUMERIC_STD.ALL;

4
> 

5
> entity fifo is

6
>   generic(

7
>     B: natural := 8;  -- Number of bits

8
>     W: natural := 4    -- Number of address bits

9
>   );

10
>   port(

11
>     clk, rst: in std_logic;

12
>     rd, wr: in std_logic;

13
>     w_data: in std_logic_vector(B-1 downto 0);

14
>     empty, full: out std_logic;

15
>     r_data: out std_logic_vector(B-1 downto 0)

16
>   );

>
> do u mean the w to change to 5? this is the number of adress bits in
> fifo ..
>
> add it already the number of bits is 8

B have to be 8. This is 8bit -> 1byte

I mean W.
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