Hi, I need to write a VHDL code on FPGA side that can receive data from a UART port and write them to a SDRAM and send back that data to a UART port. a software is on the computer side that send and receive data. BUT, I do not have a board to test. I need to write a testbench to test my design. my problem is: how can I communicate between Testbench and my software on the Windows? I need my Testbench read and write on a UART port.
VHDL Testbench can read and write from a file.
Mostafa S. wrote: > I need my Testbench read and write on a UART port. Do you really need such a thing? Or do you just want it, until you have real hardware? I've never seen something like that, and of course it is VERY tricky, because a computer terminal runs in real time. And your simulation runs in calculated time tics. E.g. if theres much to calculate a millisecond in simulation takes one second in real time. So your simulation in this case is 1000 times to slow for the comunication with the terminal software. I see it as a reasonable challenge to get such a thing running. > I need my Testbench read and write on a UART port. What is "a UART port" here? Is it the TX and RX register of the UART? Or is it a double buffered UART? As already said usually a testbench gets values from a file and it writes results to a file. And all of that with no relation to real time...
Lothar M. wrote: > Mostafa S. wrote: >> I need my Testbench read and write on a UART port. > Do you really need such a thing? Or do you just want it, until you > have real hardware? > I've never seen something like that, and of course it is VERY tricky, for Lothar: I have written an Ethernet port in my simulation. This is very tricky.
So you are looking for a kind of bridging between your test bench and a virtual UART interface on the PC. This is mainly a question of simulator support, since you have a kind of co-simulation here. To my knowledge, only a few simulators support that. As proposed above, you may emulate this interface by redirecting the UART data to files (one for sending, one for receiving) in the test bench as well as on the PC. This sounds complicated and I am in doubt if this is necessary for such a simple design. Moreover, you cannot simulate the impact of the real interface hardware. You should do the verification in two levels: Level 1 is the low level UART communication and memory interfacing. Write a simple test bench here consisting of your design and verified UART and SDRAM simulation models. Let them communicate and check that reading and writing of data packet works. If possible, do a timing simulation. Level 2 requires the target hardware. Here check if your PC software works together with the design on the real FPGA target. This is mainly a verification that your software is working correctly, but this is nothing that requires to be checked within a test bench environment.
Hi, Google for Co-Simulation. There are plenty of tools out there, but some cost real money. If you want it cheap, check GHDL and GHDLEX, this includes a virtual com port (via unix pipes) to connect to your simulation. You need a fast machine though, a full SoC and UART simulation will result in very few effective bytes per second (depending on the UART baud rate). You can skip the async UART counterpart of course and use the pipe directly. GHDLEX has a few more virtual interfaces as virtual FIFOs, they might be more effective for fast data I/O. For Windows though, you need Linux to compile, as ghdl/ghdlex won't compile your simulation natively for Windows for various reasons. This is not trivial and you're pretty much on your own there. You can also run co-simulation from Python/myHDL, you might also want to check cocotb. Greetings, - Strubi