Hi everyone. I'm having problem comparing two unsigned same length 
std_logic_vectors. I'm using the std_logic_unsigned package which 
contains a set of comparison functions for same length std_logic_vectors 
including the function below:

function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN

Here's my code:
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity main_code is
  Port ( clk : in  STD_LOGIC;
         output : out  std_logic_vector (7 downto 0);
         ero : buffer  std_logic_vector (7 downto 0) := (others => '1')
        );
end main_code;


architecture Behavioral of main_code is

signal address: std_logic_vector(3 downto 0) := (others => '0');
signal dout_rom: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');

--- component declaration (rom_core was generated by ISE core generator)
COMPONENT rom_core
  PORT (
    clka : IN STD_LOGIC ;
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;
---

begin

------ port map
your_instance_name : rom_core
  PORT MAP (
    clka => clk,
    addra => address,
    douta => dout_rom
  );
-----

output <= dout_rom;

process(clk)
begin
          if(clk'event and clk='0') then
      address <= address + 1;
    end if;

end process;

if (dout_rom < ero) then   -- line 83
ero_sig <= dout_rom;
end if;   -- line 85

end Behavioral;
----------------------------------------------------------------------

and here are the errors I get:

Line 83: Syntax error near "if".
Line 85: Syntax error near "if".

The rest of the code (the code minus the last if-clause) is compiled 
successfully. I can't figure the errors out. I would be really pleased 
to hear from you.