Hi there. I'm trying to write a code for a homework problem that will change the lights in an imaginary traffic light when a car pulls up to the red light. I'm just stumped. I'm not sure how to program a module to step through states. Thanks.
What kind of code are you supposed to write? Is it a programming language, or in asm, or for a PLC, or just an UML Diagram?
Ah, sorry. That's some important information I neglected. It's supposed to be a verilog module and test bench.
You also neglected all the other information you could provide so someone can help you. What don't you know? What did you try? What did not work? Do you have sample code you wrote? You didn't even post the complete task description, so even if someone would want to help you without you doing any prior work or having thoughts nobody could do it. You already mentioned all keywords to google. "State Machine", "Verilog", "Module", "Testbench". Sorry, I do not intend to offend or insult you, it is just that you insult some people in treating their time so invaluable so they have to do all the thinking you are supposed to do. Best Regards
I have searched Google, and none of it makes any sense. I need to program a module in Verilog to step through the red-green-yellow states of a traffic light on clock pulses. I don't know how to do this. I don't know how to start.
What you have to read is all you can find about "state machines". You Start your counter when a car arrives, when it reaches its value you change the state.
Well, then try learning HDL. A good start may be http://www.xilinx.com/support/university/vivado/vivado-teaching-material/hdl-design.html
The sequence, how a traffic light changes, changes from country to country. So it is impossible to say: The sequence. The sequence of witch country you mean?
Actually this is a pretty common task. What is your problem with the results you got? Do you know the basics of verilog?
It is hard to help you from an unknown state of knowledge. Do you know the basics of digital design? Do you know verilog? Maybe a first step to get the task out of your mind and on paper. Go to Wikipedia and search for "Finite-state machine". Go to point 1, have a look at the example and try to draw, write or somehow formulate the task. I always like and recommend a state diagram. When you have that formulated you should have a look into the basics of verilog. With the keywords "state machine" and "verilog" you should be able to finde pleeeeenty of examples. Transfer your diagram into one of those. Voila! Doesn't seem so hard, does it? Good luck, and if you have any specific questions you are welcome to ask again. (Just try to solve it on your own first, problem solving is a very important skill)
Thanks for giving me someplace to start. :) I got some code down (attached), but it's not doing what I thought it would. Specifically, this part:
1 | if (Y == 1) begin |
2 | repeat (2) begin |
3 | @ (posedge clk) |
4 | highway = 3'b010; gravel = 3'b100; |
5 | end |
6 | repeat (3) begin |
7 | @ (posedge clk) |
8 | highway = 3'b100; gravel = 3'b001; |
9 | end |
10 | repeat (2) begin |
11 | @ (posedge clk) |
12 | highway = 3'b100; gravel = 3'b010; |
13 | end |
14 | begin |
15 | @ (posedge clk) |
16 | highway = 3'b001; gravel = 3'b100; |
17 | end |
18 | end |
What I wanted it to do was sit for two clock pulses, change the lights, sit for three pulses, change the lights, and so on. What happens in my testbench is that it changes once, and then the simulation ends after the next pulse. Thanks again.
Nevermind. I got it. I don't what I was doing wrong, but it was a problem running the simulation and I fixed it. Thank you everyone for all your guidance!
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