Hi Everyone, This is my first question in the forum. I am having a challenge in the FPGA code I am trying to solve. The FPGA state machine will lock up to a certain unknown state due to the noise from SMPS. Only reset can recover it. Now I am suspect this was due to my incorrect reset code (I am new to FPGA verilog ). My question is what would possibly happen if I write the reset in this form. The reset is triggered by external signal and will be synchronized for global reset.
delay <= 0;
if (inc_delay & !reset)
delay <= delay + 1'b1;
If you have question or something I did not clarify. Please let me know.