Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you.
Hi Ashuuu, first: the sensitivity list in your module "selectsig" is wrong. The whole process is only related to the clock. So only the clock should be in the list. Second: in your testbench. First you assert s0, then you assert s1 -> what happens with s0 in that case? Best regards, derLars
Hi derLars, Do you mean s0, s1, and s0 are output, not the input?
You got what you designed. In your testbench you set s0, s1, s2 to: 0,0,0 then 0,0,1 then 0,1,1 then 1,1,1 Which gives as result in your statemachine: 000 100 110 Don' care. If you want different outputs you have to set them. PS, it seems that you get the desired output by just concatenate the input bits in the right oder.