3 bit output

Ashuuu Guest 2016-05-03 15:57 #4565648

Rate this post

•	▲ useful ▼ not useful

Hello,

I need to design 3 bit output, which are 000, 001, 010, 011, 100 using 
FPGA. I have already designed it. But, the problem is I can't get that 
desired output I want. I got 000, 001, 011 and 111 outputs. Here I 
attach my code and testbench and also Isim simulator waveform part.

Thank you.

Attached files:

selectsig.vhd (1.47 KB) | highlighted code
selectsig_tb.vhd (2.34 KB) | highlighted code
simulator.wcfg (1.85 KB)

3_bit_output.JPG (230 KB)

Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post

derLars Guest 2016-05-03 16:13 #4565671

Rate this post

•	▲ useful ▼ not useful

Hi Ashuuu,

first: the sensitivity list in your module "selectsig" is wrong. The 
whole process is only related to the clock. So only the clock should be 
in the list.

Second: in your testbench. First you assert s0, then you assert s1 -> 
what happens with s0 in that case?

Best regards,
derLars

Reply Quote Edit Delete Report post

Ashuuu Guest 2016-05-03 16:50 #4565721

Rate this post

•	▲ useful ▼ not useful

Hi derLars,

Do you mean s0, s1, and s0 are output, not the input?

Reply Quote Edit Delete Report post

Chris Guest 2016-05-03 22:24 #4566165

Rate this post

•	▲ useful ▼ not useful

You got what you designed.
In your testbench you set s0, s1, s2 to:
0,0,0 then
0,0,1 then
0,1,1 then
1,1,1

Which gives as result in your statemachine:
000
100
110
Don' care.

If you want different outputs you have to set them.

PS, it seems that  you get the desired output by just concatenate the 
input bits in the right oder.