Complexity of systems implemented using FPGA's are exponentially growing 
in a rapid pace. As a result of it most of the common design issues that 
a designer come across with ASIC SoC are becoming relevant with FPGA as 
well.  Beginning with the Virtex 4 and now with Zynq UltraSoc, there is 
considerable processing power on the compute side.  A simple migration 
is in insufficient to achieve the same performance as discrete chips. 
Estimating or identification of system performance and crucial 
bottlenecks much before writing RTL not just reduces the development 
time but also increases the Quality of Results. During this event we 
will be talking about how performance analysis and architecture 
exploration  in the early stage of system development ensures that you 
select the right FPGA platform and achieve optimal partitioning of the 
application onto the fabric. These system level models generally do not 
need the implementation level details such as the application software, 
pin level connectivity and detailed signal data. The models developed at 
this stage can be used for product specification development in order to 
select the right platform, end-to-end latency, hardware and software 
partitioning.

In this Webinar, we shall demonstrate the performance with various 
hardware-software partitions for variety of user cases and workloads. 
We shall also look at the latency time and the power consumed for 
different configurations of buffering, DDR memory interface and 
FPGA-FPGA synchronization.

Takeaways:

1. Detection of synchronization errors with system-level modeling

2. Performance improvement using the on-FPGA processors such as PowerPC 
and ARM
3. Partitioning the application or protocol between the soft-core 
processors and Fabric
4. Memory controller algorithm for control algorithms
5. Determine the utilization and effective throughput across the 
hardware resources

Webinar provides significant information on the deciding factors while 
selecting a FPGA or designing complex FPGA systems and also significance 
of system level design explorations much before RTL development. This 
webinar will be of interest for System Architects, Senior Hardware 
Engineers and Senior FPGA design engineers.

To register, http://mirabilisdesign.com/new/webinar-registration/