vhdl program of a digital clock & who have ideas to add button pls

OP (Company: eddinne) #4573889
Rate this post
useful
not useful
two button one to switch and other to increment
---------------------------------------------

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity horloge is
port (clk1 : in std_logic;
      scan : out std_logic_vector(5 downto 0);
      seg1 : out std_logic_vector(6 downto 0));
end horloge;

--Les entrés sorties interne de l’architecteur --

architecture data_flow of horloge is
signal S1,S2,M1,M2,H1,H2 : std_logic_vector (3 downto 0);
signal tps : std_logic_vector (23 downto 0);
signal s : std_logic_vector(3 downto 0);
signal count : integer range 0 to 5;
signal count1 : integer :=1;
signal clk2   : std_logic :='0';

  --deviseur de frequence (utilisé une fréquence de 1MHz et un conteur 
pour assurer l’affichage contenue sur les afficheurs 7seg) --

begin
process(clk1)
begin
if(clk1'event and clk1='1') then
count1 <=count1+1;
if(count1=500000) then
  clk2<= not clk2;
  count1<= 1;
end if ;
 count <=count+1;
  if (count=5) then
   count<=0;
end if ;
case count is
when 0 => S <= tps (3 downto 0) ;
   scan<="100000";
when 1 => S <= tps (7 downto 4) ;
   scan<="010000";
when 2 => S <= tps (11 downto 8) ;
   scan<="001000";
when 3 => S <= tps (15 downto 12) ;
   scan<="000100";
when 4 => S <= tps (19 downto 16) ;
   scan<="000010";
when 5 => S <= tps (23 downto 20) ;
   scan<="000001";
end case;
end if;
end process;

-- lincrementation (ce code on a incrémenté les secondes, Les minutes et 
les heures) --

process (clk2)
begin
if clk2'event and clk2= '1' then
      S1<=S1+1;
     if S1>"1000" then
           s2<=S2+1;
           S1<="0000";
      if S2>"0100" then
           s1<="0000";
           S2<="0000";
           M1<=M1+1;
      if M1>"1000" then
           M2<= M2+1;
           M1<="0000";
      if M2>"0100" then
           H1<= H1+1;
           M1<="0000";
           M2<="0000";
      if H1>"1000" then
           H2<= H2+1;
           M1<="0000";
       if H2>"0100" then
           H1<="0000";
           H2<="0000";
end if ;
end if ;
end if ;
end if ;
end if ;
end if ;
  tps<= S1&S2&M1&M2&H1&H2;
end if ;
end process;

-- l'afficheur 7seg --
seg1<= "1111110" when S="0000" else
       "0110000" when S="0001" else
       "1101101" when S="0010" else
       "1111001" when S="0011" else
       "0110011" when S="0100" else
       "1011011" when S="0101" else
       "1011111" when S="0110" else
       "1110000" when S="0111" else
       "1111111" when S="1000" else
       "1111011" when S="1001" else
       "1111110";
end data_flow;
Guest #4574167
Rate this post
useful
not useful
Saif S. wrote:
> use ieee.std_logic_unsigned.all;
> use ieee.numeric_std.all;
> use ieee.std_logic_arith.all;
1. Use only the numeric_std, don't mix it!
1
If possible, use ieee.numeric_std instead of the non-standard Synopsys
2
packages. However, note that numeric_std requires STD_LOGIC_VECTORs to be 
3
converted to SIGNED or UNSIGNED before applying any arithmetic operations on 
4
them (see also Sections 4.2.40, 4.8.1 and 4.11). (A better solution is to 
5
operate internally on SIGNED or UNSIGNED vectors as appropriate and convert 
6
only as necessary at the interfaces.
Source: 
https://tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#compare_conflict

> if(count1=500000) then
>   clk2<= not clk2;
2. Don't generate clocks like this;
Generate clock enables!

> two button
3. Where are the buttons?
I put my button signals in the port section of the entity description.
Don't forget to debounce.

Duke

Reply

Please log in before posting.

or

Log in with Google account

Registration is free and takes only a minute.

Register now