1 | ______|``|________________________|``|_______ ---->enable input |

2 | ________________________________________________ |

3 | _______<0><1><2><3><4><5><5><5><5><0><1><2><3><4> ---->counter output |

hello leute, i need your suggestions. i need to design a synthesizable up counter which starts counting if it finds enable signal toggling from one to zero..and once count limit is reached, it has to wait for next enable pulse to start the next counting cycle again.