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upcounter with enable signal for one clock cycle
von felix89 (Guest)

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1
______|``|________________________|``|_______       ---->enable input

2
________________________________________________

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_______<0><1><2><3><4><5><5><5><5><0><1><2><3><4>  ---->counter output


hello leute,

i need your suggestions. i need to design a synthesizable up counter 
which starts counting if it finds enable signal toggling from one to 
zero..and  once count limit is reached, it has to wait for next enable 
pulse to start the next counting cycle again.

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Re: upcounter with enable signal for one clock cycle
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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felix89 wrote:
> i need your suggestions. i need to design a synthesizable up counter
> which starts counting if it finds enable signal toggling from one to
> zero..
What language?
What target?
Whats the counting clock?
Whats the system clock?


BTW: do you know the German forum?
https://www.mikrocontroller.net/forum/fpga-vhdl-cpld
Maybe you want to switch over ther?

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Re: upcounter with enable signal for one clock cycle
von felix89 (Guest)

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vhdl,starix,same clock

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Re: upcounter with enable signal for one clock cycle
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Thats it:
1
:

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signal olden : std_logic := '0';

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signal cnt   : integer range 0 to 99 := 0;

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:

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:

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process begin

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   wait until rising_edge(clk);

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   if (olden='0' and en='1') then -- "rising edge" of enable input

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      cnt <= 0;

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   elsif (cnt<99)                 -- saturate counter at 99

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      cnt <= cnt+1;

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   end if;

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   olden <= en;                   -- remember "last" enable value

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end process;


If the enable input is a async signal one flipflop stage (at least) 
must be added for syncing to the system clock:
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:

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signal ensr  : std_logic_vector (1 downto 0) := "00";

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signal cnt   : integer range 0 to 99 := 0;

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:

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:

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process begin

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   wait until rising_edge(clk);

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   if (ensr="01") then   -- "rising edge" of enable input

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      cnt <= 0;

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   elsif (cnt<99)        -- saturate counter at 99

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      cnt <= cnt+1;

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   end if;

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   ensr <= ensr(0) & en; -- shift register for syncing and edge detection

14
end process;

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Re: upcounter with enable signal for one clock cycle
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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If the enable is synchronous and active for only one clock cycle, then 
it is extremely simple:
1
:

2
signal cnt   : integer range 0 to 99 := 0;

3
:

4
:

5
process begin

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   wait until rising_edge(clk);

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   if (en='1') then -- restart on enable signal

8
      cnt <= 0;

9
   elsif (cnt<99)                 -- saturate counter at 99

10
      cnt <= cnt+1;

11
   end if;

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end process;

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Re: upcounter with enable signal for one clock cycle
von Chris (Guest)

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Even if this is just a finger exercise, mostly it doesn't (really) help 
people if you do their homework.

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Re: upcounter with enable signal for one clock cycle
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Chris wrote:
> it doesn't (really) help people if you do their homework.
I could have written half a book, but I think, felix89 learns more by 
comparing those 3 solutions...

And additionally felix89 will ask himself (or he max be asked by his 
teacher) why the "wait until" is used here. And to find that answer will 
be a nice learning process too...

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