Hi guys,

I have a little problem with a division in VHDL. More exactly , my 
problem is that my first element which I want to be divided is not 
memorised and I really don`t know why because I have no problem with the 
second one.

Let me explain you :

I want to divide broj1 by broj2. Below is the code , please help me ! 
Thanks.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity Multiplier is
port ( input : in std_logic_vector(7 downto 0);
            btn1,btn2,btn3 : in std_logic;
            output,remainder : out std_logic_vector(7 downto 0));

end Multiplier;

architecture Behavioral of Multiplier is
signal broj1:std_logic_vector (7 downto 0);
signal broj2:std_logic_vector (7 downto 0);
signal i:std_logic_vector (7 downto 0);
signal aux:std_logic_vector (7 downto 0);
begin

process (btn1, btn2)
begin

if (btn1'event and btn1='1') then
        broj1<=input;
end if;

if (btn2'event and btn2='1') then
        broj2<=input;
end if;
end process;

process (btn3)
begin

if (btn3'event and btn3='1') then
  --output <= broj1 / broj2;

  i<="00000000";


    while (broj1>= 0) loop
        i<=i+1;
    aux<=broj1;
    broj1<=broj1-broj2;
    end loop;
  i<=i-1;
  output<=i;
  remainder<=aux;



end if;
end process;

end Behavioral;