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Subject Author Replies Last post
Alliance CAD tool VHDL problem yaser fathy 0
Read audio file in Verilog Ani Ka 6
high speed buffer/driver voltage translator E.P 2
sht25 - humidity sensor simulation model Amir Shpiler 1
audio recorder and playback in virtex 5 kelili 2
Matrix input Bahare Moradi 7
VHDL complex memory array code Omar Rashad 2
adding counter to stepper moudle saud 0
Trigonometric functions jeorges FrenchRivera 5
high speed video development board Verilogi 0
Discouraged use of latches in CPLD/FPGA logic Element Green 5
VGA problem in Verilog Xavier Pacheco 2
help: make the clock divider twice as fast or 2 Hz. johnsa 7
getting started with fpga bebel 12
Lattice MachXO2 EFB block Venkatesh Raju 3
adc and dac does not work fine togather Bilal Ahmad 0
verilog error Ahmadsyazwan Syazwan 0
LPC2148 Pulse width demultiplexer using CAP0.0 Noel Le Moult 5
Design tool for a NOC Slim Hmidi 3
Verilog error - can`t find solution Alexandru Chiser 9
Ring Oscillator with Feedback Katta Satish 8
Place 30-574 Poor placement for routing between an IO pin and BUFG tj anderson 3
How to call function on case statement (Verilog)? Monlak U. 1
Reload an ELF File Andreas Klettner 11
Need Help: A small problem in Clang Phong Pham 5
Help Beginner Make Stop watch John 3
Interfacing EFB (UFM) with Mico8 Wishbone Reto B. 8
I want to make sound with DE2 and Verilog HELP ME Aiko Yuri 37
Verilog VGA Out Xavier Pacheco 1
For loop in VHDL Chris Regform 5
Help for a beginner. ... ... 5
TWI(I2C) Interfacing for initializing OLED Microdisplay Shivashankar M N 0
AD Wandler/ FPGA - SPI Kommunikation David_tu 8
simple serial number converter Mattaaaaaaaaaaaa Aaaaaaaaaaaaaaaaa 2
Switch from USER-Mode to SVC-Mode via SWI Andreas Klettner 0
Routing limits in fpga design henry 2
i need help in problem 2 please Kaily Kai 1
Multiple DDR3 Controllers in Stratix V Antony Mathew 3
Dual-port RAM jeorges FrenchRivera 6
Arm STM32F0 Discovery PORT C Problem PeterP 2
STM32F0 Discovery Port C Pin 1 and Pin 2 problem PeterP 0
Looking to understand intra assignment delays mavericknik 1
RFM02 - not receiving nIRQ interrupt signal DarkSavior 4
Ring Oscilator in VHDL RO 8
Synth 8-1031 "Varible" is not declared, when using "Varible" in an if statement TJ 4
interleaver/deinterleaver Maryam Zilaie 5
Z-Source-Inverter Sven 31
about array and their usage as matrix Manpreet Singh 2
Timing constrains wont affect path Noam 1
DS1305 and vhdl Max Fed 3
Asynchronous mutex and arbiter Charles Effiong 1