Forum: FPGA, VHDL & Verilog audio recorder and playback in virtex 5

von kelili (Guest)

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Hi everybody,

I want to have the RTL schematic of recorder modul, for this i used IP 
CORE GENERATOR of fifo and bram modul.
I have a probleme with fifo modul i didn't have the same ports like in 
the RTL  SCHEMATIC of recorder modul.
someone can help me?

von Verilogi (Guest)

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where do the modules come from?

von P. K. (pek)

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Maybe its just a difference in the abstraction levels. You should 
discuss that with the one who specified the task...


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