Verilog error - can`t find solution

I can not add a clock in this. I must somehow count the output 
(nr_black) whenever i find out that nr is higher or equal than 2. I 
can`t add a clock. I need to do this without a CLK

Your Code:
>output [3:0] nr_black);
The Errormessage:
>It gives me this error: "Procedural assignment to a non-register
>nr_black is not permitted, left-hand side should be
>reg/integer/time/genvar" on line 46

Just do what the error mesage says:

output reg [3:0] nr_black);

Done! Now this error showed up:

"Target <nr_black> of concurrent assignment or output port connection 
should be a net type." on line 28

Line 28: assign nr_black = 4'b0000;

Initial assignment by reset will do the trick:
http://stackoverflow.com/questions/10005411/assign-a-synthesizable-initial-value-to-a-reg-in-verilog

Best regards

I tried to make nr_black wire, and then initialize a wire [3:0] counter.

And when nr>=2 counter = counter + 1. And at the end: assign nr_black = 
counter.

but it gives me this error: Procedural assignment to a non-register 
counter is not permitted, left-hand side should be 
reg/integer/time/genvar

I can`t figure it out...

It's a difference what (reg/wire) can be assigned within an
always @ (*) begin block and what beside such a block:

   blocking assignment vrs. non-blocking assignment

Maybe this helps:
http://www.asic-world.com/tidbits/wire_reg.html

Yet, i can`t make it work. I made it reg / wire, added another wire to 
count and then assign the output = counter. Nothing works...