EmbDev.net

Forum: FPGA, VHDL & Verilog Verilog error - can`t find solution


Verilog error - can`t find solution
von Alexandru C. (xeyow)

Rate this post
• ▲ useful
▼ not useful 
I have this code:

1
`timescale 1ns / 1ps

2
3
module blacks(input [31:0] b, 

4
    input left,

5
    output [3:0] nr_black);

6
7
integer i = 0;

8
integer nr;

9
assign nr_black = 4'b0000;

10
11
always @ (*) begin

12
  if(left==0)

13
  begin  

14
    while (i < 31)

15
    begin

16
      if (b[i] == 0)

17
        i=i+1;

18
      else

19
      begin

20
        nr=0;

21
        while (b[i] == 1)

22
        begin

23
          i=i+1;

24
          nr=nr+1;

25
        end

26
        if (nr >= 2)

27
          nr_black = nr_black + 4'b0001;

28
      end

29
    end

30
  end

31
  else;

32
end

33
34
endmodule


It gives me this error: "Procedural assignment to a non-register 
nr_black is not permitted, left-hand side should be 
reg/integer/time/genvar" on line 46

line 46 is this one: nr_black = nr_black + 4'b0001. How can i fix this 
program?

My nr_black is the output on 4 bits, and whenever nr is higher or equal 
than 2, i want to increment nr_black with 1. How do i do that? TY

  


  



  

  
:
    Edited by User
  

  


  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Alexandru Chiser wrote:
> How can i fix this program?
You must add a clock to your design. At the moment you have a 
combinatorial loop (in theory a counter running at maximum speed, in 
reality a noise generator). And such a thing is nearly useless...

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Alexandru C.
        (xeyow)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
I can not add a clock in this. I must somehow count the output 
(nr_black) whenever i find out that nr is higher or equal than 2. I 
can`t add a clock. I need to do this without a CLK

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        bko (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Your Code:
>output [3:0] nr_black);
The Errormessage:
>It gives me this error: "Procedural assignment to a non-register
>nr_black is not permitted, left-hand side should be
>reg/integer/time/genvar" on line 46

Just do what the error mesage says:

output reg [3:0] nr_black);

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Alexandru C.
        (xeyow)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Done! Now this error showed up:

"Target <nr_black> of concurrent assignment or output port connection 
should be a net type." on line 28

Line 28: assign nr_black = 4'b0000;

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        fpgakuechle (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Initial assignment by reset will do the trick:
http://stackoverflow.com/questions/10005411/assign-a-synthesizable-initial-value-to-a-reg-in-verilog

Best regards

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Alexandru C.
        (xeyow)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
I tried to make nr_black wire, and then initialize a wire [3:0] counter.

And when nr>=2 counter = counter + 1. And at the end: assign nr_black = 
counter.

but it gives me this error: Procedural assignment to a non-register 
counter is not permitted, left-hand side should be 
reg/integer/time/genvar

I can`t figure it out...

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        fpgakuechle (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
It's a difference what (reg/wire) can be assigned within an
always @ (*) begin block and what beside such a block:

   blocking assignment vrs. non-blocking assignment

Maybe this helps:
http://www.asic-world.com/tidbits/wire_reg.html

  


  




  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Long T.
            (Company: Ha Noi- Vietnam)
        (longtv)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Hi  Alexandru Chiser !

you only edit "output [3:0] nr_black" into "output reg  [3:0] nr_black"

your code when compiled it make circuit combination, but you used " 
alway" so output you is used, it used in "always" must be " reg" not 
"wire". My english is not good, that i written make you difficult 
understand, if you want to call me, skype: tv_long.

  


  



  

  
:
    Edited by User
  

  


  

    Report post Edit Delete Quote selected text Reply Reply with quote
  







      

      



  

    Re: Verilog error - can`t find solution
  


  

    

      von
      
        Alexandru C.
        (xeyow)
        
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Yet, i can`t make it work. I made it reg / wire, added another wire to 
count and then assign the output = counter. Nothing works...

  


  



  

  
:
    Edited by User
  

  


  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.