I have this code:
`timescale 1ns / 1ps module blacks(input [31:0] b, input left, output [3:0] nr_black); integer i = 0; integer nr; assign nr_black = 4'b0000; always @ (*) begin if(left==0) begin while (i < 31) begin if (b[i] == 0) i=i+1; else begin nr=0; while (b[i] == 1) begin i=i+1; nr=nr+1; end if (nr >= 2) nr_black = nr_black + 4'b0001; end end end else; end endmodule |
It gives me this error: "Procedural assignment to a non-register nr_black is not permitted, left-hand side should be reg/integer/time/genvar" on line 46 line 46 is this one: nr_black = nr_black + 4'b0001. How can i fix this program? My nr_black is the output on 4 bits, and whenever nr is higher or equal than 2, i want to increment nr_black with 1. How do i do that? TY
:
Edited by User
Alexandru Chiser wrote: > How can i fix this program? You must add a clock to your design. At the moment you have a combinatorial loop (in theory a counter running at maximum speed, in reality a noise generator). And such a thing is nearly useless...
I can not add a clock in this. I must somehow count the output (nr_black) whenever i find out that nr is higher or equal than 2. I can`t add a clock. I need to do this without a CLK
Your Code: >output [3:0] nr_black); The Errormessage: >It gives me this error: "Procedural assignment to a non-register >nr_black is not permitted, left-hand side should be >reg/integer/time/genvar" on line 46 Just do what the error mesage says: output reg [3:0] nr_black);
Done! Now this error showed up: "Target <nr_black> of concurrent assignment or output port connection should be a net type." on line 28 Line 28: assign nr_black = 4'b0000;
Initial assignment by reset will do the trick: http://stackoverflow.com/questions/10005411/assign-a-synthesizable-initial-value-to-a-reg-in-verilog Best regards
I tried to make nr_black wire, and then initialize a wire [3:0] counter. And when nr>=2 counter = counter + 1. And at the end: assign nr_black = counter. but it gives me this error: Procedural assignment to a non-register counter is not permitted, left-hand side should be reg/integer/time/genvar I can`t figure it out...
It's a difference what (reg/wire) can be assigned within an always @ (*) begin block and what beside such a block: blocking assignment vrs. non-blocking assignment Maybe this helps: http://www.asic-world.com/tidbits/wire_reg.html
Hi Alexandru Chiser ! you only edit "output [3:0] nr_black" into "output reg [3:0] nr_black" your code when compiled it make circuit combination, but you used " alway" so output you is used, it used in "always" must be " reg" not "wire". My english is not good, that i written make you difficult understand, if you want to call me, skype: tv_long.
:
Edited by User
Yet, i can`t make it work. I made it reg / wire, added another wire to count and then assign the output = counter. Nothing works...
:
Edited by User
Watch this topic
Disable multi-page view