Somebody with Altera Active Serial Configuration Experience may shed some light on this query I am trying to figure out whether the DCLK from Altera Stratix V FPGA will be continuously available to Active Serial Chip (EPCQ256) , if Serial Flash Loader Ip is added with my Design. OR is it enabled only when the JTAG chain is trying to write a new configuration file (.jic) via Serial Flash Loader in FPGA. I am using the internal Oscillator (100Mhz) of Stratix V for DCLK (ie CLKUSR is not utilised). Kindly share your thoughts...
: Edited by User