I'm an italian student, so I apologize for my english, and I'm new in
the forum, I have to do an exercise: the creation by MSF of a 5-bit
counter using VHDL.
I have various input signals: a STOP signal which stops the count at the
moment, a RESTART signal that resume the count, an UP_DOWN signal to
choose the direction of the count and the signal of RESET.
I have alse 3 output signals: a signal END_C which indicates the end of
the count, a signal START_C which indicates the start and a Q signal
which indicates the value of the count.
This is my VHDL code:
The compilation is successful but I get an error in model sim which is:
#**Error: (vsim-3601) Iteration limit reached at time 15ns.
I suppose there is a loop that does not allow proper execution.
Can you help me fix it? Thanks you.
Ok so i have an infinite loop but how can I move the counter into a
cloked process?? Can you please write me a couple of code strings,
because this is the first time I realze a MSF using VHDL and I'm not
practical with it??
Edoardo Bernardi wrote:> I tried to move the counter into a> cloked process in different way but anything worked.
What exactly is not working? How does your code look like now, and what
error messages do you get?
Achim S. wrote:> What exactly is not working?
With the code above the counter forms a (gated) combinatorial loop.
Edoardo Bernardi wrote:> Anyway how can I solve my problem?
If you wnat to use the 2 process style (1 clocked for the flipflops plus
1 combinatorial), then you must implement a counter_present and a
counter_next, as you did already for the FSM.
Keep in mind: even each counter is a finite state machine with defined.
First some hints:
1. Why do your states have such indifferent names like ST0, ST1, ST2,
Use SPEAKING names for your own data type.
2. And think about clever identation. It helps reading and understanding
source code very much.
3. Do NOT use std_logic_vectors for calculations:
No one knows whether this calculation above is signed or unsigned...
4. "up_down" is a stupid name for a signal. Does it mean the counter
counts UP and DOWN at the same time? Or what? Is '0' = UP or is '1' =
5. "when others =>"
In your own type stato there is no other sate! All of the 4 states
ST!..4 are explicitly decoded in the case. So: why "when others"?
But if I had to do that job with using of a FSM for the counter
management, this could be my result:
Lothar Miller wrote:> With the code above the counter forms a (gated) combinatorial loop.
that's true, and in fact I had phrased my question wrongly. What I
really wanted to know was how the actual code looks like and what
error messages Edoardo gets, after he moved the counter to a clocked
Achim S. wrote:> how the actual code looks like and what error messages Edoardo gets,> after he moved the counter to a clocked process.
Indeed, the latest code and its problems may be of interest here... ;-)