VHDL, MSF 5 bit counter

Edoardo B. OP #4121197
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Hello everyone,
I'm an italian student, so I apologize for my english, and I'm new in 
the forum, I have to do an exercise: the creation by MSF of a 5-bit 
counter using VHDL.
I have various input signals: a STOP signal which stops the count at the 
moment, a RESTART signal that resume the count, an UP_DOWN signal to 
choose the direction of the count and the signal of RESET.
I have alse 3 output signals: a signal END_C which indicates the end of 
the count, a signal START_C which indicates the start and a Q signal 
which indicates the value of the count.
This is my VHDL code:

1
library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;

4


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entity esercizio3 is

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port(CK, stop, restart, reset, up_down: in std_logic;

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       end_c, start_c: out std_logic;

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      Q: out std_logic_vector(4 downto 0));

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end esercizio3;

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architecture arc of esercizio3 is

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    type stato is(ST0, ST1, ST2, ST3);

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    signal ps, ns: stato;

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    signal temp: std_logic_vector(4 downto 0);

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    begin

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      seq_proc: process(CK, RESET)

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       begin

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        if(RESET='0')then

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        ps<=ST0;

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        elsif(rising_edge(CK)) then

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        ps<=ns;

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        end if;

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      end process seq_proc;

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      comb_proc:process(RESTART, STOP, UP_DOWN, PS)

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      begin

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      end_c<='0';

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      start_c<='0';

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       case ps is

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       when ST0=>

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         temp<="00000";

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         if(stop='0')then

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         ns<=ST0;

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         elsif(up_down='0')then

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         ns<=ST1;

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         else

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         ns<=ST2;

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         end if;

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      when ST1=>

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        temp<=temp-"00001";

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        if(stop='0')then

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        ns<=ST3;

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        elsif(up_down='0')then

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        ns<=ST1;

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        else

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        ns<=ST2;

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        end if;

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     when ST2=>

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        temp<=temp+"00001";

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        if(stop='0')then

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        ns<=ST3;

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        elsif(up_down<='0')then

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        ns<=ST1;

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        else

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        ns<=ST2;

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        end if;

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     when ST3=>

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        if(Restart='1')then

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        ns<=ST3;

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        elsif(up_down='0')then

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        ns<=ST1;

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        else

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        ns<=ST2;

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        end if;

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        when others=>

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        ns<=ST0;

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     end case;

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     Q<=temp;

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     if(temp="00000")then

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     start_c<='1';

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     elsif(temp="11111")then

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     end_c<='1';

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     end if;

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   end process comb_proc;

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end arc;


The compilation is successful but I get an error in model sim which is:

#**Error: (vsim-3601) Iteration limit reached at time 15ns.

I suppose there is a loop that does not allow proper execution.
Can you help me fix it? Thanks you.
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Lothar M. Moderator (Company: Titel) #4124000
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Achim S. wrote:
> What exactly is not working?
With the code above the counter forms a (gated) combinatorial loop.

Edoardo Bernardi wrote:
> Anyway how can I solve my problem?
If you wnat to use the 2 process style (1 clocked for the flipflops plus 
1 combinatorial), then you must implement a counter_present and a 
counter_next, as you did already for the FSM.
Keep in mind: even each counter is a finite state machine with defined.

First some hints:
1. Why do your states have such indifferent names like ST0, ST1, ST2, 
ST3?
Use SPEAKING names for your own data type.

2. And think about clever identation. It helps reading and understanding 
source code very much.

3. Do NOT use std_logic_vectors for calculations:
1
    signal temp: std_logic_vector(4 downto 0);

2
    :

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        temp<=temp-"00001";

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    :

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        temp<=temp+"00001";

No one knows whether this calculation above is signed or unsigned...

4. "up_down" is a stupid name for a signal. Does it mean the counter 
counts UP and DOWN at the same time? Or what? Is '0' = UP or is '1' = 
UP?

5. "when others =>"
In your own type stato there is no other sate! All of the 4 states 
ST!..4 are explicitly decoded in the case. So: why "when others"?


But if I had to do that job with using of a FSM for the counter 
management, this could be my result:
1
library ieee;

2
use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

4


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entity esercizio3 is

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port(CK, stop, restart, reset, up_down: in std_logic;

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     end_c, start_c: out std_logic;

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     Q: out std_logic_vector(4 downto 0)

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    );

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end esercizio3;

11


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architecture arc of esercizio3 is

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  type stato is(IDLE, COUNT);

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  signal state: stato;

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  signal cnt: integer range 0 to 31;

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begin

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   seq_proc: process(CK)

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   begin

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      if rising_edge(CK) then

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         case state is

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            when IDLE =>

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               if restart='1' then

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                  state <= COUNT;

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               end if;

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            when COUNT =>

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               if up_down='0' then  -- count UP

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                  if cnt=31 then  cnt <= 0; -- overflow

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                  else            cnt <= cnt+1;

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                  end if;

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               else                 -- count DOWN

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                  if cnt=0 then  cnt <= 31; -- underflow

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                  else           cnt <= cnt-1;

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                  end if;

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               end if;

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               if stop='1' then

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                  state <= IDLE;

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               end if;

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         end case;

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         -- handle the reset as a synchronous signal

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         if reset='1' then

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            cnt <= 0;

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            state <= IDLE;

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         end if;

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      end if;

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   end process;

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   -- some concurrent assignments

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   Q <= std_logic_vector(to_unsigned(cnt,5));   

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   start_c <= '1' when cnt=0  else '0';

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   end_c   <= '1' when cnt=31 else '0';

54


55
end arc;
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Achim S. Guest #4124082
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Lothar Miller wrote:
> With the code above the counter forms a (gated) combinatorial loop.

that's true, and in fact I had phrased my question wrongly. What I 
really wanted to know was how the actual code looks like and what 
error messages Edoardo gets, after he moved the counter to a clocked 
process.
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