# Forum: FPGA, VHDL & Verilog help: make the clock divider twice as fast or 2 Hz.

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Hello
This is one part of school assignment that trying to figure it out. I
have done the rest parts but I'm stuck at this one:

"This given module take the 50 MHz clock_50 of the DE2 board and divides
down to generate a CLKout of 1 Hz. Modify this given module to make the
clock twice as fast or 2 Hz"

and here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DIVIDER is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end DIVIDER;

architecture behavioral of DIVIDER is
signal count: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,count,reset)
begin
if(reset='1') then count<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then count <=count+1;
if (count = 25000000) then temp <= NOT temp; count<=0;
end if;
end if;
CLKout<= temp;
end process;
end behavioral;

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this is a very funny school because they are using old synopsis libs
which are outdated and they use "temp" as a signal name where there is

Then it uses asnch clocking and a user signal inside the clocked part in
the sensitvity list

This code is wimmeling for errors...

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ok but do you know how to answer the question?

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This shouldn't be that hard for you. Try to figure out how the 50 MHz
(Hint: 50000000 Hz) is divided to get 1 Hz. Then alter this to get twice
as much clock changes as before.
1 Hz means one full period per second which means two changes in
polarity per second.

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so i should change 25000000 to 50000000?

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ohh i got it i should change it to 12500000. is that right?

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All of those numbers are wrong!!
A counter from 0 to 10 counts 11 steps. So a counter from 0 to 25000000
counts 25000001 steps. That's simply and basically wrong.

So to get 2 Hz a counter must count from 0 to 12499999 and then the
output must be toggled.

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a toogle is not a good indicator for a clock, better us only one small
tick at 2499999

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