Hello
This is one part of school assignment that trying to figure it out. I 
have done the rest parts but I'm stuck at this one:

"This given module take the 50 MHz clock_50 of the DE2 board and divides 
down to generate a CLKout of 1 Hz. Modify this given module to make the 
clock twice as fast or 2 Hz"

and here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DIVIDER is
port ( CLKin: in std_logic;
reset: in std_logic;
CLKout: out std_logic);
end DIVIDER;

architecture behavioral of DIVIDER is
signal count: integer:=0;
signal temp : std_logic := '1';
begin
process(CLKin,count,reset)
begin
if(reset='1') then count<=0; temp<='1';
elsif(CLKin'event and CLKin='1') then count <=count+1;
if (count = 25000000) then temp <= NOT temp; count<=0;
end if;
end if;
CLKout<= temp;
end process;
end behavioral;