Hi,
I'm trying to use the M9K memory block of my FPGA cyclone IV.
For that purpose I use the Mega-wizard of Quartus II 10.1sp1 Web
Edition.
I implemented the 1 port RAM with single clock, the entity generated
looks like the code below:
1 | entity RAM_1Port IS
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2 | PORT
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3 | (
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4 | address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
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5 | clock : IN STD_LOGIC := '1';
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6 | data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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7 | wren : IN STD_LOGIC ;
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8 | q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
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9 | );
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10 | END RAM_1Port ;
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.
To test this memory, i have created the code below:
1 | -- Instantiate the RAM single port mode
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2 | RAM1: RAM_1Port port map(RAM_address,CLOCK_50,RAM_data_IN,RAM_wren,Output_RAM);
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3 |
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4 | test: process(CLOCK_50,KEY) -- asynchonos process
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5 | begin
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6 |
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7 | IF (KEY='0') THEN -- when reset is selected
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8 |
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9 | -- init signals RAM Single port
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10 | wr_address <=(others => '0');
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11 | RAM_address<=(others =>'0');
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12 | RAM_data_IN<=(others =>'0');
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13 | RAM_wren<='0';
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14 | Write_Ok<='0';
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15 | ELSIF(rising_edge(CLOCK_50)) then
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16 |
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17 | if(Write_Ok='0') then -- start writing
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18 |
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19 | RAM_wren<='1';
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20 |
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21 | RAM_address<=std_logic_vector(to_unsigned(10, 5));
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22 | RAM_data_IN<=std_logic_vector(to_unsigned(1984, 16));
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23 | cpt<=cpt+1;
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24 |
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25 | if(cpt=1) then
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26 | Write_Ok<='1';
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27 | cpt<=0;
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28 | end if;
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29 | end if;
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30 |
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31 | if(Write_Ok='1') then --start reading
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32 |
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33 | RAM_wren<='0';
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34 | RAM_address<=std_logic_vector(to_unsigned(10, 5));
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35 | cpt<=cpt+1;
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36 | RAM_out<=Output_RAM;
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37 |
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38 | if(cpt=1) then
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39 | Write_Ok<='0';
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40 | cpt<=0;
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41 | end if;
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42 | end if;
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43 | end if;
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44 | end process;
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45 | END;
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The problem i have is that the output RAM_out is always zero, i don't
understand why.
Can you help on this please if you have an idea?
Best regards
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