Hey guys, I've an university project in which I have to design a reaction timer in VHDL - you've to use the led on the fpga as a visual stimulus and the time should appear on the display... How many vhd files am I going to need and which ones? P.s. - I have to use finite state machines... Thanks a lot.
Michael C wrote: > How many vhd files am I going to need I would say: 1 file is enough... > and which ones? Those one that describes the behaviour of a reaction timer in the necessary and synthesizable way. > P.s. - I have to use finite state machines... Of course, because each simple counter is a FSM. And a clock consists of several counters... Have a look at this stop watch, its not to far away from a reaction timer: http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html (Try Google translator, its German)