Hi all,

 Perhaps someone who has experience in Lattice EFB may answer this.



 I am building a design on a MachXO2 using the EFB for I2C MASTER
 communication

 I built my own state machine for writing and reading to the wishbone
 bus.

I Could able to read/write EFB I2C Master to I2C slave external device.

the actual problem is when we flash the FPGA to work properly(i mean to 
say for successful read/write operation in I2C doesn't happen unless we 
give power on reset)

since our our requirement is to flash the FPGA and use it.. there is no 
provision of giving power on reset in actual application.

When we give power on reset it works flawlessly after flash but it 
doesn't work when we flash the fpga and use before giving the power on 
reset.

when i probed the I2C lines after flashing the FPGA and before giving 
power on reset. a write / read leads to continuous generation of SCL and 
No data SDA.


same logic works flawlessly after giving power on reset.

Am i missing something here.. Any help would be very helpful...
Thanks....

Actually we tried this option , generating the reset signal and giving 
to the EFB module din't worked.

I2C hard ip in EFB module always need power on reset after flashing for 
a proper functioning. otherwise it I2C clock pulses are coming 
continuously.