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Forum: FPGA, VHDL & Verilog outputs is unutilized


von had (Guest)


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the buttonOut, flipflops and temporal is un-utilized after the frequency 
divider process is added into the codes..
I couldn't figure out the problem as I'm new to vhdl..
my codes is as below..

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity debounce is
  --counter size (19 bits gives 10.5ms with 50MHz clock)
  generic ( counter_size  :  INTEGER := 4); 
  port( clk       : in  std_logic;  --input clock
        buttonIn  : in  std_logic;  --input signal to be debounced
        buttonOut : out std_logic); --debounced signal
end debounce;

architecture debounce of debounce is
  
  signal flipflops   : std_logic_vector(1 downto 0); --input flip flops
  signal counter_set : std_logic ;                    --sync reset to zero
  
  signal temporal: std_logic;
  signal counter : integer range 0 to 124999 := 0; --counter size(200Hz)
      
  begin

  counter_set <= flipflops(0) xor flipflops(1);--check when to start/reset counter 
  
  --freqeuncy divider process
  process (clk) begin
    if rising_edge(clk) then
      if (counter = 124999) then --Condition met
        temporal <= not(temporal);
        counter <= 0;
      else                       --Condition not met
        counter <= counter + 1;
      end if;
    end if;
  end process;
  
  --debounce process
  process(temporal)
  begin
    if(rising_edge(temporal)) then
      flipflops(0) <= buttonIn;
      flipflops(1) <= flipflops(0);
      buttonOut <= flipflops(1);
    end if;
  end process; 
  
end debounce;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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had wrote:
> temporal <= not(temporal);
This is NOT a way to generate a clock inside a FPGA. Check out how to 
generate and use a "clock enable".

von Lothar M. (lkmiller) (Moderator)


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had wrote:
> the buttonOut, flipflops and temporal is un-utilized after the frequency
> divider process is added into the codes..
How do you see this? What target and what toolchain is used? What is the 
exact error message or warning?

von VHDL hotline (Guest)


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Initialize/reset temporal. If you simulate it: not(U) is U and there is 
never a rising edge of temporal, so fliflops and buttonout are never 
assigned.

As Lothar said, use a clock enable or if the complete functionality are 
only these two processes, just add the fliflops/buttonout assignment 
directly to your first process and discard the second one, so the 
counter value itself is your clock enable.

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