library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity debounce is

  --counter size (19 bits gives 10.5ms with 50MHz clock)

  generic ( counter_size  :  INTEGER := 4); 

  port( clk       : in  std_logic;  --input clock

        buttonIn  : in  std_logic;  --input signal to be debounced

        buttonOut : out std_logic); --debounced signal

end debounce;

architecture debounce of debounce is

  signal flipflops   : std_logic_vector(1 downto 0); --input flip flops

  signal counter_set : std_logic ;                    --sync reset to zero

  signal temporal: std_logic;

  signal counter : integer range 0 to 124999 := 0; --counter size(200Hz)

  begin

  counter_set <= flipflops(0) xor flipflops(1);--check when to start/reset counter 

  --freqeuncy divider process

  process (clk) begin

    if rising_edge(clk) then

      if (counter = 124999) then --Condition met

        temporal <= not(temporal);

        counter <= 0;

      else                       --Condition not met

        counter <= counter + 1;

      end if;

    end if;

  end process;

  --debounce process

  process(temporal)

  begin

    if(rising_edge(temporal)) then

      flipflops(0) <= buttonIn;

      flipflops(1) <= flipflops(0);

      buttonOut <= flipflops(1);

    end if;

  end process; 

end debounce;