Forum: FPGA, VHDL & Verilog VHDL : 4-Bit Adder and Subtractor Problem

von Mahmood M. (mahmood_m)

Rate this post
0 useful
not useful
i have some trouble with designing an 4-bit adder and subtracter in VHDL
i posted in stackoverflow about my problem , but no answer yet !
the post is here , with codes , image and notes :

help me solve that problems

von matthias (Guest)

Rate this post
0 useful
not useful
I didn't checked if the algorithm itself is correct, but in your 
testbench for example the signal 'sum'& 'E' isn't in the sensitivity 
list. All signals that can change and are on the right side or in an 
if-comparison etc must be listed in the sensitivity list to ensure that 
the Simulator can calculate the new signals.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.