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Forum: FPGA, VHDL & Verilog Place 30-574 Poor placement for routing between an IO pin and BUFG


von tj anderson (Guest)


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`timescale 1ns / 1ps    
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    module stopwatch(
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        input clock,
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        input reset,
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        input increment,
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        input start,
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        output [6:0] seg,
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        output dp,
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        output [3:0] an
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        );
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        reg [3:0] reg_d0, reg_d1, reg_d2, reg_d3; //registers that will hold the individual counts
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        reg [22:0] ticker;
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        wire click;
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        //the mod 1kHz clock to generate a tick ever 0.001 second
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        always @ (posedge (clock) or posedge (reset))
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        begin
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            if(reset)
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            begin
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                ticker <= 0;
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            end
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            else 
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            begin
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                if (start)
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                begin
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                    if(ticker == (100000 - 1)) //if it reaches the desired max value reset it
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                        ticker <= 0;
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                    else if (increment)
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                        ticker <= ticker;
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                    else
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                        ticker <= ticker + 1;
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                end 
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            end
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        end
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        //increment a second everytime rising edge of down button
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        reg [3:0] inc_temp;
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        always @ (posedge (increment)) 
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        begin
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            if (reg_d3 == 9)
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                inc_temp = 0;
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            else
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                inc_temp = reg_d3 + 1;
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        end
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        assign click = ((ticker == (100000 - 1))?1'b1:1'b0); //click to be assigned high every 0.001 second
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        //update data start from here
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        always @ (posedge (clock) or posedge (reset))
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        begin
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            if(reset)
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            begin
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                reg_d0 <= 0;
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                reg_d1 <= 0;
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                reg_d2 <= 0;
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                reg_d3 <= 0;
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            end
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            else
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            begin
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                if (increment)
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                    begin
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                        reg_d3 <= inc_temp;
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                        reg_d0 <= reg_d0;
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                        reg_d1 <= reg_d1;
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                        reg_d2 <= reg_d2;    
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                    end
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                    else if (click) //increment at every click
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                    begin
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                        if(reg_d0 == 9) //xxx9 - 1th milisecond
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                        begin
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                            reg_d0 <= 0;
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                            if (reg_d1 == 9) //xx99 - 10th milisecond
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                            begin
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                                reg_d1 <= 0;
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                                if (reg_d2 == 9) //x999 - 100th milisecond
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                                begin
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                                    reg_d2 <= 0;
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                                    if(reg_d3 == 9) //9999 - The second digit
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                                        reg_d3 <= 0;
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                                    else
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                                        reg_d3 <= reg_d3 + 1;
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                                end
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                                else
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                                    reg_d2 <= reg_d2 + 1;
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                            end
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                            else
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                                reg_d1 <= reg_d1 + 1;
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                        end
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                        else
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                            reg_d0 <= reg_d0 + 1;
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                    end
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                    else
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                    begin
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                        reg_d3 <= reg_d3;
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                        reg_d0 <= reg_d0;
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                        reg_d1 <= reg_d1;
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                        reg_d2 <= reg_d2;
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                    end
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            end
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        end
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        //Mux for display 4 7segs LEDs
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        localparam N = 18; 
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        reg [N-1:0]count;
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        always @ (posedge clock or posedge reset)
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        begin
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            if (reset)
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                count <= 0;
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            else
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                count <= count + 1;
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        end
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        reg [6:0]sseg;
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        reg [3:0]an_temp;
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        reg reg_dp;
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        always @ (*)
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            begin
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                case(count[N-1:N-2])
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                    2'b00 :
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                    begin
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                        sseg = reg_d0;
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                        an_temp = 4'b1110;
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                        reg_dp = 1'b1;
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                    end
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                    2'b01:
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                    begin
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                        sseg = reg_d1;
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                        an_temp = 4'b1101;
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                        reg_dp = 1'b0;
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                    end
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                    2'b10:
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                    begin
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                        sseg = reg_d2;
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                        an_temp = 4'b1011;
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                        reg_dp = 1'b1;
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                    end
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                    2'b11:
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                    begin
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                        sseg = reg_d3;
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                        an_temp = 4'b0111;
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                        reg_dp = 1'b0;
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                    end
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                endcase
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            end
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        assign an = an_temp;
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        //update the data to display to LEDs
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        reg [6:0] sseg_temp;
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        always @ (*)
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        begin
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            case(sseg)
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                4'd0 : sseg_temp = 7'b1000000;
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                4'd1 : sseg_temp = 7'b1111001;
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                4'd2 : sseg_temp = 7'b0100100;
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                4'd3 : sseg_temp = 7'b0110000;
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                4'd4 : sseg_temp = 7'b0011001;
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                4'd5 : sseg_temp = 7'b0010010;
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                4'd6 : sseg_temp = 7'b0000010;
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                4'd7 : sseg_temp = 7'b1111000;
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                4'd8 : sseg_temp = 7'b0000000;
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                4'd9 : sseg_temp = 7'b0010000;
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                default : sseg_temp = 7'b0111111; //dash
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            endcase
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        end
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        assign seg = sseg_temp;
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        assign dp = reg_dp;
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    endmodule

I'm trying to design a stop watch, but i'm stuck at the increment thing. 
The intend is when I press `increment`(a button) the `reg_d3` will 
increment by one and hold it state until the button is release. I'm able 
to make the clock stop when the button is pressed, but I can't update 
the `reg_d3`. I always receive `[Place 30-574] Poor placement for 
routing between an IO pin and BUFG`. I don't know why, I use increment 
in the clkdivider just find. Please help me. Thanks

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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The problem is this here:
> when I press `increment`(a button)
>  always @ (posedge (increment))

This is VERY BAD design practise due to a bunch of reasons:
1. every mechanical switch bounces, so you will get
   some undefined clock pulses every keypress

2. you add an asynchronous clock domain to your design

3. every asynchronous signal (e.g. switch, sensor...)
   must be synchronized to your systems clock

4. you use a non dedicated pin for a clock signal

BTW: number 4 is the tiniest problem in your design, although it is the 
reason for you error message...

My major hints for your designs are:
A. use only one clock throughout the whole design
B. every external signal must be synchronized to that clock with 2 
flipflops

tj anderson wrote:
> I'm trying to design a stop watch
So, not just copy a code from a place even your teacher knows very 
well 
(http://simplefpga.blogspot.de/2012/07/to-code-stopwatch-in-verilog.html), 
but at least try to understand, what happens there. And then find the 
right place to dig a hole for your buttons (after adding a sync stage 
and an edge detection to them)...

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