EmbDev.net

Forum: FPGA, VHDL & Verilog verilog error


verilog error
von Ahmadsyazwan S. (syazwan)

Rate this post
0 ▲ useful
▼ not useful 
module controlunit control_path 
(opcode,outA,carry,reset,pc_sel,pc_wrt,addr_sel,
ir_wrt,data_sel,rega_sel,
reg_wrt,opb_sel,opa_sel,
alu_sel,re,we,clk);


 Error (10170): Verilog HDL syntax error at controlunit.v(3) near text 
"control_path";  expecting ";"

please help me solve this error.

: Edited by User
Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.