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Forum: FPGA, VHDL & Verilog Decoder 3:8 simulation with out test bench


Author: Sayeed (Guest)
Posted on:

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Hi

I need a help to simulate decode  VHDL core in ISIM.

Regards
Sayeed

Author: Lothar Miller (lkmiller) (Moderator)
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Sayeed wrote:
> I need a help to simulate decode  VHDL core in ISIM.
And what is your actual problem? How far do you get? And what problems 
do you encounter? What is your specific 3:8 decoder doing? And how 
does your decoder "core" look like?

Author: alexinho (Guest)
Posted on:
Attached files:
  • CID.v (2.51 KB, 181 downloads)

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Please do not delet that!

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