Forum: FPGA, VHDL & Verilog Synthesize problem

von Bahare M. (bahare)

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Dear friend, can any one tell me what is the problem with My division 
I have attached it!!!!!!!!!!!

von fpgakuechle (Guest)

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for i in n downto 0 loop
    if (temp1>=temp2 * 2**i) then
power of two from a non-constant is not synthesizable,

Best to:
* throw away your code
* read working VHD -code i.e. 
*synthesize that and check reports and rtl/structutal view
*draw block schematic of your implementation
*rewrite synthesizable code from the scratch

Best regards,


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