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Subject
Author
Replies
Last post
Spi Flash AT45DB321
Chris Customchris
11
2016-05-03 08:44
Error in shift operator
Hayder Al-Amily
0
2016-05-02 23:50
8x1 Multiplexer
Min_ah
7
2016-05-02 20:20
LPC2138 ADC example
Thomas Fernando
12
2016-05-02 17:50
Memory Interface with a Muxed Address/Data Bus
Max
3
2016-05-02 15:34
Altium NB3000
Moorthi
2
2016-04-30 13:50
An overall PWM system by using FPGA
_Jaiko007
5
2016-04-30 11:01
initialization of EBR based ROM in Lattice MachXO2
Thomas Hergenhahn
1
2016-04-30 04:56
reading 24bit with I2S on nucleo stm32f411re
Mike
0
2016-04-28 14:32
STM32F407 SPI reads wrong data
Mirko
1
2016-04-27 13:05
Automated Verilog Module Instantiation
Sauhaarda Chowdhuri
0
2016-04-26 05:37
Machx02 User Flash Memory
Chris Customchris
6
2016-04-25 08:57
Blocking vs Non-blocking questions (verilog)
Trevor Hill
1
2016-04-20 21:58
8 bit DIVISION PROBLEM
Marius Pop
1
2016-04-20 17:41
VHDL parsing tool
Bartlomiej T.
0
2016-04-20 14:35
Foucault pendulum with drive by an electromagnet used as a clock
Jeremias
5
2016-04-19 20:03
How to compare equivalent gate count, power consumption and possibly area and delay of circuits?
Rohan Narkhede
0
2016-04-18 15:57
BASYS 2 Implementation
Nirav Bhatt
2
2016-04-16 00:30
UART in FPGA for receiver
rushin
27
2016-04-15 20:29
Problem of Rom & sensitivity list
Ed Hut
15
2016-04-14 07:38
VHDL : signal goes to zero when looping on a state
Ed Hut
11
2016-04-11 22:12
Synchronizing reset signal used as a combinational logic
Robert
3
2016-04-11 11:26
16bit synchronous counter
Ber 25
7
2016-04-10 15:37
upcounter with enable signal for one clock cycle
felix89
6
2016-04-09 13:39
Clock port and any other port of a register should not be driven by the same signal source
Robert
3
2016-04-08 16:21
STM32F303 Discovery: SPI basics
Harald
1
2016-04-06 20:39
Efficiently test HMIs?
BennieMa
0
2016-04-06 17:54
Availability of JTAG
M_A AF
1
2016-04-06 13:58
Get Binary-Data from Wav-File
Samuel_Schmid
18
2016-04-06 08:18
VHDL UART testbench that send/receive to/from a software on the Windows
Mostafa Semofa
8
2016-04-04 17:16
VHDL Button Debouncing
Matt
18
2016-04-01 21:08
Altera Quartus Design Assistant Critical Warnings
Robert
1
2016-03-31 14:44
Data acquisition
jeorges FrenchRivera
3
2016-03-29 15:22
modified booth encoder
Pavithra Kodada
7
2016-03-26 17:22
FPGA Frequency Divider
_Jaiko 007
2
2016-03-26 17:04
Dual processor Microblaze
Ramzi Hmaidi
0
2016-03-26 10:53
Six Key Strategies To Make PCB Work Smarter
Jenny Gao
0
2016-03-25 08:40
Incorrect reset in verilog
Z. W.
3
2016-03-23 16:49
Vhdl file reading: reading integer(varying length) and converting to std_logic_vector
felix89
1
2016-03-22 14:15
system identification with lms using microphone
Radhika Krishnan
0
2016-03-16 13:20
Change a front of clock signal
Dima Ustinoff
3
2016-03-15 23:48
[newbie] chip select - unexpected result?
Kenny Millar
3
2016-03-15 10:46
Rpm detector vhdl
ChrisChris
7
2016-03-14 12:22
Writing to bmi160 register fails
Aditya K.
0
2016-03-14 09:38
LPC1768 Set GPIO using EMAC
Prakash Rajolli
9
2016-03-12 21:26
vhdl reading text file finding current line number?
felix89
6
2016-03-11 13:35
4 bit up down counter with a programmable modulo value
Ahmed Alibrahim
8
2016-03-11 12:07
Build an I2C protocol using systemverilog
Fitrahhadi S.
3
2016-03-10 05:15
Multi-core simulation in Modelsim
Dima Ustinoff
2
2016-03-09 22:22
Frequency Divider using VHDL
_Jaiko 007
5
2016-03-09 19:49
Verilog buffer implementation problem
H Karim
1
2016-03-09 06:36
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