# Forum: µC & Digital Electronics Data acquisition

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Hi everyone,

I have a square signal at the output of a photodetector. The frequency
of this signal is MHz. It's a noisy signal.
First of all, i want to sample this signal with and ADC (fs=10 MHz, 14
bit). Then filter the signal converted to recover the original signal
without noise.

Can someone help me about choosing the best platform to that( FPGA, µC,

I need also you help concerning the choice of the ADC.

Best regards

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jeorges F. wrote:
> First of all, i want to sample this signal with and ADC (fs=10 MHz, 14
> bit). Then filter the signal converted to recover the original signal
> without noise.

Hello jeorges,

are you sure you require this performance? The converters for this task
are not cheap (around 30USD per piece) and so is the input stage for the
converter. Next is the performance for "filtering" such a data stream in
reatime.
Can you describe the problem a little more to check whether other
solutions would be easier?

rgds

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jeorges F. wrote:
> to recover the original signal without noise.
Is the original signal "noiseless"? Where does it come from?
Which part of the signal chain is noisy?
What must be done with the signal afterwards?

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thank you for you answers Lothar & 6a66.

This is the description of the problem:

the purpose of the system is to treat a sinusoidal input signal,
attenuated and noisy so as to output a signal of the same frequency but
having a high ratio of signal to noise. the output of this system will
provide a square wave.

The input is a sinusoidal signal e(t) of frequency fr, marred by
predominantly Gaussian noise and possibly having a DC component.
This signal has the form :
e (t) = A (t) sin (fr.t) + n (t) (A (t) amplitude of the signal, n (t)
is the additive Gaussian noise and DC (t) the DC component).
- e(t) is an analog signal supplied by a photodiode and a mounting
Transimpedance.
The features  of e(t)are :
-5 V <e (t) <+ 5V
A (t)> 20 mV
SNR> 5 dB
Fr = 1 MHz

The goal is to have a square frequency analog output signal, compatible
logic level (0 V and 3.3 V low state high State)
the phase difference between e(t) and s(t) should remain relatively
constant with a phase noise less than 0.05 °.

Best regards

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