EmbDev.net

Topics in all forums



Subject Author Replies Last post
UART in FPGA for receiver rushin 27
Problem of Rom & sensitivity list Ed Hut 15
VHDL : signal goes to zero when looping on a state Ed Hut 11
Synchronizing reset signal used as a combinational logic Robert 3
16bit synchronous counter Ber 25 7
upcounter with enable signal for one clock cycle felix89 6
Clock port and any other port of a register should not be driven by the same signal source Robert 3
STM32F303 Discovery: SPI basics Harald 1
locked Efficiently test HMIs? BennieMa 0
Availability of JTAG M_A AF 1
locked Get Binary-Data from Wav-File Samuel_Schmid 18
VHDL UART testbench that send/receive to/from a software on the Windows Mostafa Semofa 8
VHDL Button Debouncing Matt 18
Altera Quartus Design Assistant Critical Warnings Robert 1
Data acquisition jeorges FrenchRivera 3
modified booth encoder Pavithra Kodada 7
FPGA Frequency Divider _Jaiko 007 2
Dual processor Microblaze Ramzi Hmaidi 0
Six Key Strategies To Make PCB Work Smarter Jenny Gao 0
Incorrect reset in verilog Z. W. 3
Vhdl file reading: reading integer(varying length) and converting to std_logic_vector felix89 1
system identification with lms using microphone Radhika Krishnan 0
Change a front of clock signal Dima Ustinoff 3
[newbie] chip select - unexpected result? Kenny Millar 3
Rpm detector vhdl ChrisChris 7
Writing to bmi160 register fails Aditya K. 0
LPC1768 Set GPIO using EMAC Prakash Rajolli 9
vhdl reading text file finding current line number? felix89 6
4 bit up down counter with a programmable modulo value Ahmed Alibrahim 8
Build an I2C protocol using systemverilog Fitrahhadi S. 3
Multi-core simulation in Modelsim Dima Ustinoff 2
Frequency Divider using VHDL _Jaiko 007 5
Verilog buffer implementation problem H Karim 1
Implement filter in verilog Qq Qq 1
USB Logic Analyzer Mayank Chaudhary 4
CORDIC(Coordinate Rotation Digital Computer) CJU 3
troubles with VHDL testbench in Modelsim Dima Ustinoff 1
General variables Antonio Angelino 0
LUT in verilog Antonio Angelino 4
Linking libspeeex in coocox Shashi Abd 1
parallel data into serial rushin 1
Can't understand Verilog arithmetics Ubix2014 2
WS2000 Regenmesser Lupo01 1
VHDL with ModelSim and Quartus II Rogério Clynton Ribeiro 0
locked GCC ARM Embedded -> Compiler bug! Dereferenzing of Pointers. Ma Hi 2
VHDl for a custom CLB Johnny 0
Proof of concept: ATmega MP3 decoder Horst 1
STM32F0 and 1Mbit EEprom Jens Wörmann 0
Hello world on Atlys Spartan-6 xc6slx45 Slim Hmidi 3
Problems in constraining Negative setup slack Glen 3
lpc2148 and uart Ranjeeth P t 4