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Subject
Author
Replies
Last post
system identification with lms using microphone
Radhika Krishnan
0
2016-03-16 13:20
Change a front of clock signal
Dima Ustinoff
3
2016-03-15 23:48
[newbie] chip select - unexpected result?
Kenny Millar
3
2016-03-15 10:46
Rpm detector vhdl
ChrisChris
7
2016-03-14 12:22
Writing to bmi160 register fails
Aditya K.
0
2016-03-14 09:38
LPC1768 Set GPIO using EMAC
Prakash Rajolli
9
2016-03-12 21:26
vhdl reading text file finding current line number?
felix89
6
2016-03-11 13:35
4 bit up down counter with a programmable modulo value
Ahmed Alibrahim
8
2016-03-11 12:07
Build an I2C protocol using systemverilog
Fitrahhadi S.
3
2016-03-10 05:15
Multi-core simulation in Modelsim
Dima Ustinoff
2
2016-03-09 22:22
Frequency Divider using VHDL
_Jaiko 007
5
2016-03-09 19:49
Verilog buffer implementation problem
H Karim
1
2016-03-09 06:36
Implement filter in verilog
Qq Qq
1
2016-03-09 06:19
USB Logic Analyzer
Mayank Chaudhary
4
2016-03-08 08:52
CORDIC(Coordinate Rotation Digital Computer)
CJU
3
2016-03-07 08:19
troubles with VHDL testbench in Modelsim
Dima Ustinoff
1
2016-03-07 06:17
General variables
Antonio Angelino
0
2016-03-06 20:31
LUT in verilog
Antonio Angelino
4
2016-03-06 19:51
Linking libspeeex in coocox
Shashi Abd
1
2016-03-06 16:53
parallel data into serial
rushin
1
2016-03-06 09:28
Can't understand Verilog arithmetics
Ubix2014
2
2016-03-04 14:24
WS2000 Regenmesser
Lupo01
1
2016-03-04 10:43
VHDL with ModelSim and Quartus II
Rogério Clynton Ribeiro
0
2016-03-04 04:43
GCC ARM Embedded -> Compiler bug! Dereferenzing of Pointers.
Ma Hi
2
2016-02-29 15:16
VHDl for a custom CLB
Johnny
0
2016-02-26 18:52
Proof of concept: ATmega MP3 decoder
Horst
1
2016-02-26 17:18
STM32F0 and 1Mbit EEprom
Jens Wörmann
0
2016-02-26 13:43
Hello world on Atlys Spartan-6 xc6slx45
Slim Hmidi
3
2016-02-26 12:56
Problems in constraining Negative setup slack
Glen
3
2016-02-25 17:57
lpc2148 and uart
Ranjeeth P t
4
2016-02-25 15:01
Basic Question
Elena Cososchi
2
2016-02-24 23:01
control logic for memory selection
felix89
2
2016-02-24 16:32
OV7670 camera in VHDL
jeorges FrenchRivera
6
2016-02-24 15:29
Multiple posedges in sensitivity list
Joe
6
2016-02-23 00:17
VHDL calculator matrix input help.
ed jones
1
2016-02-19 13:10
Limit current of L6206 Bridge Driver
Torsten
5
2016-02-15 03:41
Please help me in writing correct verilog test bench code for parallel crc32 with 32 bit data width
Ajit Sinam
2
2016-02-14 12:48
Arcade Centipede Game in Verilog
Asiong Martinez
11
2016-02-13 13:04
Bitwise OR of std_logic_vector
Hamidreza Ahmadian
2
2016-02-12 18:26
Inertial sensors not giving updated values
Aditya K.
0
2016-02-12 13:44
STM32F401RE GPIO
Asiong Martinez
0
2016-02-12 12:32
problem in 2d- dct computation
Ajay Mittal
1
2016-02-11 19:32
SAM7-EX256 - /bin/sh: arm-elf-as: command not found
Roslan Hristov
0
2016-02-10 16:00
FATAL_ERROR: Iteration limit 10000 is reached
Rohan Narkhede
7
2016-02-10 07:31
DCT code. Don't know why it is not working.
Ajay Mittal
2
2016-02-09 12:22
recommend me an FPGA card for networking
Nulik Nol
4
2016-02-06 02:28
User Flash Memory, Machxo2 7000HE breakout
ChrisChris
2
2016-02-05 16:47
watermarking on FPGA
Hamid Kavian
3
2016-02-04 00:28
GPS to FPGA to PC
Yuniarto Wimbo Nugroho
9
2016-02-03 09:30
shift left or shift right
deepak singh
9
2016-02-03 08:45
Altium (SVN)DbLib Add/Edit Component in Altium
Martin
6
2016-02-02 23:42
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