Hi, I'm learning VHDL and I've implemented a 16-bit microcoded CPU in VHDL using GHDL as my platform. The source code and a description of the CPU is here: http://minnie.tuhs.org/Programs/UcodeCPU I'd like to buy a FPGA development board and get the CPU into silicon. However, in the ALU I have used the VHDL arithmetic operators +, -, *, / and rem. This is cheating of a sort, as I didn't really implement any of these with real gates. When it comes to targetting an FPGA, is this going to cause problems? Am I going to have to go back and build adders, subtractors, multipliers etc.? Or can most FPGAs implement the VHDL arithmetic, albeit inefficiently? I'm not too worried about the speed of the CPU, just that it works! Many thanks in advance for your helpful feedback, Warren
+ and - can be implemented in real hardware quiet easily, they should work without problems and run very fast. For * and especially for / it is somewhat harder. No problem at all for a simulation with GHDL, but it can be kind of problem if you want to map these operations with 16 Bit width to real hardware. The logic needed to implement a 16Bit division in a single CLK-cycle can be quite large. Get a version of some FPGA development software (both Xilinx and Altera have free versions of their development systems). Try not only to translate your code, but to implement it on some (virtual) FPGA. Even if you do not yet have any real FPGA available, the development system will tell you, if it would be able to fit the logic into that hardware, how fast it would run there and how much resources it would consume. Most FPGAs have dedicated and optimized logic-Blocks just for arithemtics (called e.g. dsp48), which are present on the FPGA anyways (so not using them will not save you any ressources). They can e.g. execute a multiplicaiton for large bit widths in a single CLK-cycle at high frequency. For Division there exist typically IP-Cores, which make use of these dsp-cores and wich you may also implement in your design. They only need a few CLK-cylces for a division. (see e.g. http://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf) Using these blocks should save ressources and give you much nicer performance than the implementation of * and / with standard logic slices. But for a first try you may also keep the operations in your VHDL-code as they are and see, what the development system makes out of it and how fine it is running ;-)
Achim S. wrote: > Try not only to translate your code, but to implement it on some > (virtual) FPGA. Even if you do not yet have any real FPGA available, the > development system will tell you, if it would be able to fit the logic > into that hardware, how fast it would run there and how much resources > it would consume It does much more: if you target a specific FPGA the toolchain will generate an implementaition specific schematic. Have a look at that schematic and you will see, how much hardware is needed for the operation.
Thanks Achim and Lothar for you feedback. I'm also keen on trying out the PDP-11/70 processor on opencores.org, so I'll install and play with the Xilinx toolchain. Eventually I will buy a Nexys4 when I'm ready to try my own CPU out on a real FPGA. I'm sure I'll have more questions in the future! Thanks again. Warren