+ and - can be implemented in real hardware quiet easily, they should 
work without problems and run very fast. For * and especially for / it 
is somewhat harder. No problem at all for a simulation with GHDL, but it 
can be kind of problem if you want to map these operations with 16 Bit 
width to real hardware. The logic needed to implement a 16Bit division 
in a single CLK-cycle can be quite large.

Get a version of some FPGA development software (both Xilinx and Altera 
have free versions of their development systems). Try not only to 
translate your code, but to implement it on some (virtual) FPGA. Even if 
you do not yet have any real FPGA available, the development system will 
tell you, if it would be able to fit the logic into that hardware, how 
fast it would run there and how much resources it would consume.

Most FPGAs have dedicated and optimized logic-Blocks just for 
arithemtics (called e.g. dsp48), which are present on the FPGA anyways 
(so not using them will not save you any ressources). They can e.g. 
execute a multiplicaiton for large bit widths in a single CLK-cycle at 
high frequency. For Division there exist typically IP-Cores, which make 
use of these dsp-cores and wich you may also implement in your design. 
They only need a few CLK-cylces for a division. (see e.g. 
http://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf)

Using these blocks should save ressources and give you much nicer 
performance than the implementation of * and / with standard logic 
slices.  But for a first try you may also keep the operations in your 
VHDL-code as they are and see, what the development system makes out of 
it and how fine it is running ;-)