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Newbie question on FPGA
von Sreedev K. (arduino_guy)

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Hello,
I am using SPARTAN-6 XC6SLX9 on the mojo board.
https://embeddedmicro.com/products/mojo-v3.html
The design i'm trying to implement is a simple upcounter which counts up 
whenever a switch is pressed. The switch is active low. However, the 
always block doesn't seem to execute. Can someone point out the mistake.
The code i'm trying to run is:

module mojo_top(input xps,
    // 50MHz clock input
    input clk,
    // Input from reset button (active low)
    input rst_n,
    // cclk input from AVR, high when AVR is ready
    input cclk,
    // Outputs to the 8 onboard LEDs
    output[7:0]led,
    // AVR SPI connections
    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    // AVR ADC channel select
    output [3:0] spi_channel,
    // Serial connections
    input avr_tx, // AVR Tx => FPGA Rx
    output avr_rx, // AVR Rx => FPGA Tx
    input avr_rx_busy // AVR Rx buffer full
    );

wire rst = ~rst_n; // make reset active high

// thsignals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
reg [7:0] counts=0;
assign led=counts;


always@(negedge rst_n)
begin
counts=counts+1;
end
endmodule

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Re: Newbie question on FPGA
von andi6510 (Guest)

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In your code, which signal represents the switch that is being pressed. 
The only signal you are dealing with is the reset signal rst_n. Or do 
you want to count the number of resets? Please describe this more in 
detail otherwise nobody will be able to help you. Next question is if 
the switch signal is already debounced. If not you'd need a debouncing 
circuit as well otherwise it will count up a couple of times for each 
switch press.

An FPGA has only clocked D-flip-flops. So it's mandatory to use clocked 
(synchronous) logic. In Synchronous logic some basic code 
not_including debouncing could look like this:

module (rst, clk, keypressed, counter);

input reset;
input clk;
input keypressed;
output [7:0] counter;

reg [7;0] counter;
reg key_d1;
reg key_d2;
reg key_d3;

always @(posedge clk or negedge rst)
begin
    if (rst) begin
        counter <= 8'd0; // on reset clear all registers
        key_d1 <= 1'b0;
        key_d2 <= 1'b0;
        key_d3 <= 1'b0;
    else
        key_d1 <= keypressed; // sample input signal twice...
        key_d2 <= key_d1;     // ... to avoid metastability
        key_d3 <= key_d2;     // another delay for raising edge 
detection
        if (key_d2 & ~key_d3) begin // raising edge detection
            counter <= counter + 8'd1;
        end
    end
end

endmodule

(I just typed the code in here - no guarantee that it is running as 
is...)

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