Forum: FPGA, VHDL & Verilog Spi,Quadrature encoder combined?Insight Please

von Chris (Guest)

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Hi, I have been trying to combine 2 of the available options of my 
encoder into a cpld with vhdl, I wrote my own bit bang function to 
obtain the absolute position via spi, from here once run I would like to 
pass the 12bit angle position into "count", where the quadrature would 
pick up and start adjusting angle position according to A&B pulses and 
an index "count" reset. both of the codes when separate work perfect, 
but I cannot figure out how to join these two codes together, either 
fails from multiple signal assignment or spi section is not compiled 
correctly and "data" is trimed out. I bet its something simple, but im 
only a few months in as a hobby, with minimal background in avr/arduino. 
Current hardware is a Xilinx Xc9572xL cpld and a 64macrocell Coolrunner 
II, would preffer to have it operating on the 9572. Thank you for your 

von Lothar M. (lkmiller) (Moderator)

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What kind of problem do you encounter with the attached code?

BTW: that is a new kind of SPI, isn't it? A very new one....

Have a look for the rising_edge() function and how others use it. Who 
adds a "and CLK='1'" behind it? And why not? Because that "and CLK='1'" 
is already included in the function...

von Chris (Guest)

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My cpld is small and I have a to-do list for encoder position so I kept 
spi very light, plus it literally only needs to run once, in fact I'll 
have a 1uf capacitor and 1k resistor to an enable pin to start code 10ms 
after power on, required by encoder, and mosi is tied to vss. As for the 
clock condition, that is the code I found online and it worked, I tried 
just clk'event but (double edge detection) not supported by cpld,

von Chris (Guest)

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I tried a new if, elsif array, and it compiled successfully, but only on 
a much larger cpld, 84macro cells, looks like I may make the switch to a 
lattice ispmach series, higher frequency, higher mc count and newer 
tech. Strange that I can't find any info anywhere about spi read then 
quadrature after, especially on fpga or cpld :-\


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