mux in verilog

lkb Guest #4197507
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Hi,

I'm new to Verilog and having a problem with code for which I have 
pasted a simplified version below.

I have wired the TEST_BUS out to oscilloscope and want to look at 
signals by changing my mux select.  But what I'm seeing is that when 
cmd_reg0 changes, the output of the mux goes to all 0's.

I'm working with Xilinx FPGA.

Thanks for your help.


my IO ports
------
1
input [31:0] cmd_reg0;

2
input [31:0] cmd_reg1;

3
output [10:0] TEST_BUS;

some code
1
reg [10:0] TEST_BUS_r;

2
assign TEST_BUS = TEST_BUS_r;

3


4


5
wire [7:0] mux_cmd = cmd_reg0[7:0];

6
wire [3:0] mux_sel = cmd_reg1[3:0];

7
reg [7:0] mux_cmd_r;

8
reg [3:0] mux_sel_r;

9


10
always @(posedge CLK25)

11
begin

12
  mux_cmd_r <= mux_cmd;

13
  mux_sel_r <= mux_sel;

14
end

15


16
// this mux can be used for monitoring signals on oscilloscope/chipscope

17
always @( mux_cmd_r or mux_sel_r )

18
begin

19
if( mux_cmd_r == 8'h8B)

20
begin

21
   case ( mux_sel_r )

22
  4'h0 : TEST_BUS_r = { 11 bit signals concatenaed }

23
  4'h1 : TEST_BUS_r = { 11 bit signals concatenaed }

24
  4'h2 : TEST_BUS_r = { 11 bit signals concatenaed }

25
  4'h3 : TEST_BUS_r = { 11 bit signals concatenaed }

26
   endcase

27
end

28
end

-----------
some more code
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lkb Guest #4197581
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Lothar M. wrote:
> lkb wrote:
> I'm seeing is that when cmd_reg0 changes,
>
> From what to what?
>
> the output of the mux goes to all 0's.
>
> What do you expect instead?
>
> I have wired the TEST_BUS out to oscilloscope
>
> What about running this design on a testbench? Thats the firstmost step
> in HDL-Design...

If I change cmd_reg0 from 0x0000008B to 0x00000080.  The signals out to 
scope should stay based on the cmd_reg1 value. Basically the case 
statement inside if/then block is not asserted when reg0 is not 0x8B.

Yes, it works in testbench/sim, but not in hardware.  If I don't change 
value of reg0 then the signals selected are seen on the oscilloscope, as 
expected.

Thanks.
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Lothar M. Moderator (Company: Titel) #4197614
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lkb wrote:
> Yes, it works in testbench/sim, but not in hardware
I'm more the VHDL man, but as far as I see you have designed a latch, 
which is not good design practice on an FPGA. Additionally this latch 
has a combinational enable, which is far more worse and will lead to 
unpredictable behaviour. Keep in mind although all off the registers of 
mux_cmd_r change at the (nearly) same time, the wiring and the mux 
decoder logic afterwards lead to spikes and spurious latching of 
undesired values.

Additionally I assume that the mux_cmd_r is not synchronous to the 
clock and you therefore will have a problem with an inconsitent value in 
that register: what if the mux_cmd changes at the (almost) very same 
time the clock rises? Then maybe due to setup/hold-timing violation some 
of the bits take the new value, and some of them keep the old value. And 
ouch, for one clock cycle you have a wrong mux_cmd_r value. Same 
concerns the behaviour of the mux_sel_r value.

You must NOT think of the TEST_BUS_r as one singal. Inside the FPGA 
there are 12 single bits with their very own wiring and LUTs and 
behaviour...

BTW:
TEST_BUS_r is not the correct name, because its not a "r"egister. It 
should be named TEST_BUS_l from "l"atch...
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