Hello, which FPGA device is suitable for working on the topic evolvable hardware? I'm planning to use this method: 1. Generate random Bitstream 2. Load Bitstream to FPGA 3. Fitness-Test 4. Modify Bitstream via Genetic/Evolotuinary Algorithm 5. Go to Step 2. [Until perfect solution is found] I already bought a Xilinx Ml310 Development Board as shown here: http://www.xilinx.com/products/boards/ml310/current/ Unfortunately I've come to the conclusion that this device might not be a good way to start this project, because I can't find much information about bitstream-manipulation from Xilinx-FPGAs in general (I've found the tool JBits, but I can't find useful documentation nor the SDK itself). Also In the end I want to reproduce experiments like this from Dr. Adrian Thompson with his tone discriminator: http://archive.bcs.org/bulletin/jan98/leading.htm Can anyone give me some advice on which device I should buy and which lectures I should read before I start this project? I would prefer a chip which is easy in handling the bitstream manipulation, because that's what is the evolutionary process is all about. Thank you for your support and sorry for my bad english :) Sincerely, Dude
Hi Dangerous ground! Xilinx FPGAs can modify itself on the fly, but you need non-free license to the "partial reconfig" solution. if you want something OPEN SOURCE, then IceStorm has fully documented bitstream and tools for ice40 https://hackaday.io/project/6636-iced-an-arduino-style-board-with-ice-fpga I just now tested my first real FPGA design that was implemented using icestorm toolchain ICE FPGA can not directly manipulate itself at LIVE, but it could reflash one of the multiboot images and restart itself
Hello Antti Lukats, First, thank you for your fast response :) The site from IceStorm is very interesting. Where can I buy this board and how much does it cost? How long does a reflash take? Sincerely, Dude
About 20 years ago, Adrian Thompson (University of Sussex) did some interesting work in this area on (completely obsolete and no longer available) Xilinx 6216 FPGAs. For example, he evolved a circuit that was capable of distinguishing two different frequencies: http://www.damninteresting.com/on-the-origin-of-circuits/ http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.50.9691&rep=rep1&type=pdf Unfortunately, if I remember correctly, the evolved circuits turned out to include physical characteristics of the specific FPGA the GA was running on, such as propagation delays, which is probably not what you intended. Nevertheless I thought this link might be interesting. Back then, the internal structure of the 62xx FPGAs and the bitfile format was well documented (the design was acquired by Xilinx in a company take-over) and people were able to write their own synthesis tools without the need to reverse engineer anything...
Argh, somehow managed to overlook that you mentioned Adrian's work in your post. Oops.
I'm really into Antti Lukats idea. Can anyone tell me the fpga with the highest number of logic cells that can be programmed with the IceStorm Tools? I've already found this one: http://www.latticestore.com/searchresults/tabid/463/searchid/1/searchvalue/ice40hx1k-stick-evn/default.aspx But I wounder if there is any bigger FPGA whith more logic cells? Sincerely, Dude
Hi, current status of icestorm supported devices HX1K, HX8K (very likely also LP1K and LP8K) the 8K devices are the largest ICE devices. if you want LARGE reprogrammable GRID, then one option could be stuffing a lots of DIPSY style board in connected grid https://hackaday.io/project/6592-dipsy the FPGA there is very low cost and low power, so a even a rather large array would still be moderate in price. unfortunatly the UL1K is not yet supported by icestorm tools :( icestorm includes download tool to configure the ice, the protocol is very simple. SPI slave mode config is also supported, so if you want to have array that can be reconfigured fast, I would use some Xilinx ARTIX with lots of IO to spit out a lot of SPI masters that each will configure ICE devices.
Dude wrote: > 1. Generate random Bitstream > 2. Load Bitstream to FPGA > 3. Fitness-Test > 4. Modify Bitstream via Genetic/Evolotuinary Algorithm > 5. Go to Step 2. > [Until perfect solution is found] > But for complex circuits and larger FPGAs this will take a very long time, no? OK for ultra small 1k LUT FPGA it may work - but for "normal" size FPGAs?