Hello. While I was studying the theory I have got that if you write a
netlist, then you can generate a bitfile, load it into the FPGA and
execute the program. I have done a double check with my Xilinx FPGA:
-I created a VHDL program with Vivado
-I defined the constraints (link inputs and outputs of my VHDL program
to the actual pins of my FPGA) on a new file (.xdc)
-I generated the bitfile, loaded it into the FPGA and tested the program
-Finally I exported the netlist (still with Vivado) generating the .edn
Next, to check if the theory was correct I have done:
-I created a new post-synthesis project
-I imported the netlist previously generated (without the constraint
-I tried to generate the the bitfile but I got errors. I solved by
creating the constraints (.xdc).
So, my question is: is there the possibility to define the constraints
into the netlist or every time I import a netlist should I have to
create an external file in order to define the constraints?