Forum: FPGA, VHDL & Verilog Multi-width RAM access?

von Warren T. (doctorwkt)

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Hi all, after finally getting my microcoded CPU working both on GHDL and 
on a Nexys4 board, I have some questions about RAM access.

On most current micros, there are instructions that load/store data to 
the RAM at different widths, e.g. 8-, 16-, 32- and 64-bit. These also 
generally have to be aligned to the width, e.g. 32-bit accesses have to 
be on byte addresses that are multiples of four.

The question is, how is this implemented? Assume that the data bus is 
64-bits and the CPU wants to write 8-bits at location X. Is there a 
64-bit fetch, the lowest 8-bits are modified and the new 64-bits of data 
written back.

Or, is only 8-bits of new data sent down the data bus and the RAM has to 
ensure that this gets written at the correct location? Along with 
suitable control lines to tell the RAM the size of the transfer.

Or, some other mechanism?

I'm asking because my microcoded CPU only does 16-bit transfers and I 
would like to modify it to permit 8- and 16-bit transfers.

If there is a descriptive web resource on this, please pass on the 

Many thanks in advance for your help, Warren

P.S Links to my CPU implentations:

von P. K. (pek)

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I see two possible solutions you could apply:

A) Dual port RAM. This helps if you want to use two widths only (e.g. 8 
and 16-bit). You have two completely separate address and data busses. 
The address bus with the 16-bit data has one bit less (the LSB which 
needs always to be 0).
Be aware that addressing the same memory content simultaneously from 
both ports may cause trouble...

B) RAM with byte write enable. With that you can realise even more 
possibilities (e.g. 8-, 16- and 32-bit access). In this case, the 
following rules apply:
32-bit: Bit 1:0 of the address are 0, all 4 bytes are enabled
16-bit: Bit 0 the address is 0, bit 1 of the address is used
        to either enable bytes 1:0 (if 0) or bytes 3:2 (if 1).
 8-bit: Bit 1:0 of the address are directly used to enable (address) one
        of the byte enables of the word.

A) is limited to 2 widths B) extendable to even more. I don't know how 
far these are supported by FPGA IP libraries, depends on vendor. At 
least B) you can implement on any FPGA "by hand" (given sufficient 

: Edited by User


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