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Forum: FPGA, VHDL & Verilog nested ifs vs elsif

von SparkyT (Guest)

2015-07-15 13:09

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Hi all, quick question about if-else, what is the difference in 
describing the 2 counters bellow?

my_test:process (CLK, RESETn)
  -- Clear signals to default values
  if RESETn = '0' then
            addr_inc <= '0';
            load <= '0';
            trans_dec <= '0';
            address_cnt <= 0;
            transfer_cnt <= 0;
            reset_cnt <= '1';   
  -- register ...
  elsif rising_edge(CLK) then
        -- memory address counter 
        if reset_cnt = '1' then
                address_cnt <=0;           -- reset counter
        else
                if load = '1' then
                        address_cnt <= to_integer(unsigned( head(14 downto 7) ));   -- load value from header
                        if addr_inc = '1' then
                        address_cnt <= address_cnt + 1;                             -- increment by one
                end if;
        end if;
        -- memory transfer size counter 
        if reset_cnt = '1' then
                transfer_cnt <= 0;                                          -- reset counter
        elsif load = '1' then
                transfer_cnt <= to_integer(unsigned( head(6 downto 3) ));   -- load value from header
        elsif trans_dec = '1' then
                transfer_cnt <= transfer_cnt - 1;                           -- decrement by one
        end if;
  end if;
end process my_test;

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Re: nested ifs vs elsif

von Klakx (Guest)

2015-07-15 15:36

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From VHDL Point of view: nothing, maybe code readability improved

But also some Synthesizer create different multiplexer structures, where 
other Synthesizer really dont care about that.

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Re: nested ifs vs elsif

von SparkyT (Guest)

2015-07-16 12:21

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