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Subject Author Replies Last post
Polyphase filter decimator on VHDL Dmtry Karlin 17
Implementing the game Breakout in Verilog Jacob Culleny 2
Writing strings to the UART Andreas Hoeschler 2
advance information: serious USBaspLoader (+tinyUSBboard) bug Stephan B. 1
Keyboard PS/2 Door Lock - Basys 2 Ariel Coba 1
Interface AD7655 with FPGA using VHDL jeorges FrenchRivera 3
Seven Segment Display design with 2 4-1 MUXes Keith F. 1
One bit for status Raju 1
SATA controller program execution Sunayana C. 3
How to write vectors in VHDL John Smith 1
IP67 classified micro controller board with great stack of sensors. Tuomo KK 4
Upsampling of a received signal from UART Roger Swan 2
Syntax Help with Project Annon 2
dcdc Converter comparison Tim Wendler 2
fpga vhdl serial read operation Kumar 2
Someone please help me about it (!) 16x1 mux More actuals found than formals in port map Yusuf Yılmaz 1
FIR Filter Sampling Frequency Roger Swan 4
Can I get this to work in Verilog Astudentofminewhowasalittlepiggie 5
XILINX XC3S50AN: Can't program internal Flash Oerg866 5
VHDL signal assigment MohseN 4
Query on DSP4YOU AVB switch. Hrusikesh Padhy 0
sequential multiplier code for datapath and control sequence Tahir 1
ethersex pinning question /Reembox Nikki Fenton 0
Diode replacements database Douglas Pears 0
ceil and log2 functions Matt 1
UART communication through Nexys 3 Roger Swan 7
Goertzel Algorithm in Verilog / Frequency Recognition Nikita Gusev 9
VHDL fill rest of the vector in assignment Václav 4
SSD1322 - Clock Cycle Time in 8080 Parallel Mode Burkhard 3
Port Map Errors Jay JA 2
High speed FPGA design Silver 2
Printf, putc, and getc serial issues Rick Mc 1
Need help with Verilog project idea Amin 1
Altera Cyclone 3/4 DDR2 Sample Design [emi_ddr2_ciii.zip] Antony Mathew 3
VHDL process issue : double execution Sacha 17
Network on chip implementation in FPGA Bala Krishnan 2
Verilog state machine query Kenny Millar 9
DE0_NANO_ADC jeorges FrenchRivera 4
function "to_integer" Mira Miyou 9
Digital to analog converter DAC and FPGA issam sassi 0
Drive 12V 15A load with PWM 18V-48V 2A Saif Butt 0
Progam in VHDL for a ttl finder Jose Maria 0
Processing/Sampling IF(IQ) signals Himadri 1
Verilog FPGA Compatibility Charan Mehta 2
Amontec out of order? markushh 1
32-to-1 multiplexer VHDL code simplification Zoltan Preiner 2
RF class AB power amp my 1
4-Bit Structural Adder using port map Jay JA 4
VHDL Counter Problem (Please help) Icy Snow 2
warning when synthesis afsoon 2
Error when using with-select-when in VHDL Ayush Khemka 3