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Forum: FPGA, VHDL & Verilog Syntax Help with Project


von Annon (Guest)


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1
--Baseball Scorekeeper
2
--STRIKES  
3
library IEEE; 
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use ieee.std_logic_1164.all; 
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entity strikes is
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port     (button_press        : in std_logic; 
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       reset                  : in  std_logic; 
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       led_out            : out std_logic_vector (1 downto 0)
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       ); 
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end entity; 
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architecture strikes_arch of strikes is 
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signal tempLED : std_logic_vector (1 downto 0);
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begin
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  process ( button_press)
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    begin 
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    if reset='1' then tempLED <="00"; 
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        elsif rising_edge(button_press) then
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      case tempLED is 
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      when "00" => tempLED <="01"; 
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      when "01" => tempLED <="11"; 
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      when "10" => tempLED <="00"; 
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      when "11" => tempLED <="00"; 
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      when others => tempLED <= "00"; 
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        end case; 
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    end if;   
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  end process; 
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led_out <= tempLED;
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end strikes_arch;
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--BALLS
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library IEEE; 
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use ieee.std_logic_1164.all; 
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entity balls is
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port     (button_press        : in std_logic; 
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       reset             : in  std_logic; 
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       led_out            : out std_logic_vector (2 downto 0)
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       ); 
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end entity; 
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architecture balls_arch of balls is 
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signal tempLED : std_logic_vector (2 downto 0);
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begin
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  process ( button_press)
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    begin 
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    if reset='1' then tempLED <="000"; 
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        elsif rising_edge(button_press) then
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      case tempLED is 
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      when "000" => tempLED <="001"; 
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      when "001" => tempLED <="011"; 
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      when "010" => tempLED <="000"; 
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      when "011" => tempLED <="111"; 
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      when others => tempLED <= "000"; 
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        end case;
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    end if;   
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  end process; 
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led_out <= tempLED;
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end balls_arch; 
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library IEEE;
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use ieee.std_logic_1164.all; 
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entity Baseball is 
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port   ( b1, b2, b3    : in std_logic;
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      --mst_rst   : in std_logic; 
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      strikes   : out std_logic_vector (1 downto 0); 
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      balls    : out std_logic_vector (2 downto 0)
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      ); 
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end entity; 
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architecture Baseball_arch of Baseball is 
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--signal tempStrikes :  std_logic_vector (1 downto 0);
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--signal tempBalls   :  std_logic_vector (2 downto 0); 
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--signal temprst     : std_logic; 
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component strikes is
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port     (button_press        : in std_logic; 
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       reset                  : in  std_logic; 
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       led_out            : out std_logic_vector (1 downto 0)
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       ); 
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end component; 
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component balls is
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port     (button_press     : in std_logic; 
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       reset             : in  std_logic; 
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       led_out         : out std_logic_vector (2 downto 0)
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       ); 
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end component; 
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begin
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  UX0: port map strikes (button_press=> b1, reset=>b3, led_out=>strikes); 
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  UX1: port map balls   (button_press=> b2, reset=>b3, led_out=>balls ); 
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end Baseball_arch;

Error:
.
Error (10500): VHDL syntax error at Baseball.vhd(121) near text "port"; 
expecting "(", or an identifier ("port" is a reserved keyword), or a 
sequential statement
Error (10500): VHDL syntax error at Baseball.vhd(122) near text "port"; 
expecting "(", or an identifier ("port" is a reserved keyword), or a 
sequential statement

**The "port" it's referring to is in my port mapping section**
I'm not sure if it has something to do with the internal signals. 
Although, looking at my design on paper the only thing connecting the 
"strikes" and "balls" blocks together is my reset which is just tied to 
an external button (b3). Hmm..it's always something small. I'd 
appreciate a look.

Thanks.

von Lothar M. (lkmiller) (Moderator)


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This will give a wrong simuslation due to a wrong sensitivity list:
1
 process ( button_press) begin
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    if reset='1' then 
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       tempLED <="00";
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    elsif rising_edge(button_press) then
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       ...
And additionally: a button is never(!!!) a clock source. But you will 
see that in real life later on...

But your actual problem is as reported here:
  UX0: port map strikes (
And there:
  UX1: port map balls   (
Check the order of "port map" and "strikes", as well as "port map" and 
"balls"...

: Edited by Moderator
von Jay J. (jboss10)


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Thank you Lothar. You are always willing to help. I figured out what was 
wrong and was able to compile. I do understand, in a real-world 
application this should/would never be done, but for the sake of my 
project it suffices.

Question..I'm trying to figure out how to make this work so when the 
baseball count is, let's say, 3-balls and 1-strike. If the next ball is 
thrown is a "ball" then both the strikes and balls LEDs get reset back 
to "00" and "000", respectively.

Do I create another process? Or another entity entirely? I've done it 
almost 10 different ways and none of which have worked or compiled. It's 
tricky trying to get both balls and strikes to get reset when they are 
in totally different processes. I've only been coding in VHDL for maybe 
two months so bare with me.

I appreciate your help. Enjoy the holidays.

**Corrected Code:
1
--STRIKES  
2
library IEEE; 
3
use ieee.std_logic_1164.all; 
4
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entity strike is
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port     (button_press        : in std_logic; 
8
       reset                  : in  std_logic; 
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       led_out            : out std_logic_vector (1 downto 0)
10
      
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       ); 
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end entity; 
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architecture strike_arch of strike is 
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signal tempLED : std_logic_vector (1 downto 0);
16
begin
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  process ( button_press)
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    begin 
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    if reset='1' then tempLED <="00"; 
22
        elsif rising_edge(button_press) then
23
          
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      case tempLED is 
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      when "00" => tempLED <="01"; 
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      when "01" => tempLED <="11"; 
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      when "10" => tempLED <="00"; 
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      when "11" => tempLED <="00"; 
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      when others => tempLED <= "00"; 
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        end case; 
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    end if;   
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  end process; 
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led_out <= tempLED;
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end strike_arch;
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--BALLS
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library IEEE; 
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use ieee.std_logic_1164.all; 
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entity ball is
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port     (button_press        : in std_logic; 
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       reset             : in  std_logic; 
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       led_out            : out std_logic_vector (2 downto 0)
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       ); 
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end entity; 
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architecture ball_arch of ball is 
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signal tempLED : std_logic_vector (2 downto 0);
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begin
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  process ( button_press)
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    begin 
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    if reset='1' then tempLED <="000"; 
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        elsif rising_edge(button_press) then
62
          
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      case tempLED is 
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      when "000" => tempLED <="001"; 
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      when "001" => tempLED <="011"; 
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      when "010" => tempLED <="000"; 
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      when "011" => tempLED <="111"; 
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      when others => tempLED <= "000"; 
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        end case;
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    end if;   
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  end process; 
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led_out <= tempLED;
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end ball_arch; 
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library IEEE;
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use ieee.std_logic_1164.all; 
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entity Baseball is 
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port   ( b1_strikes, b2_balls, b3_hit    : in std_logic;
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      strikes   : out std_logic_vector (1 downto 0); 
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      balls    : out std_logic_vector (2 downto 0)
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      ); 
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end entity; 
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architecture Baseball_arch of Baseball is 
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--signal tempStrikes :  std_logic_vector (1 downto 0);
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--signal tempBalls   :  std_logic_vector (2 downto 0); 
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--signal temprst     : std_logic; 
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component strike is
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port     (button_press        : in std_logic; 
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       reset                  : in  std_logic; 
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       led_out            : out std_logic_vector (1 downto 0)
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       ); 
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end component; 
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component ball is
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port     (button_press     : in std_logic; 
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       reset             : in  std_logic; 
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       led_out         : out std_logic_vector (2 downto 0)
114
      
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       ); 
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end component; 
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begin
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  UX0: strike port map  (button_press=> b1_strikes, reset=>b3_hit, led_out=>strikes); 
122
  UX1: ball port map    (button_press=> b2_balls, reset=>b3_hit, led_out=>balls); 
123
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end Baseball_arch;

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