Errors I'm receiving:
"type of formal parameter "internal" does not match type or value"
"object "S" is used but not declared"
"cannot associate formal port "internal" of mode "object" with an
..same errors trickle down with tempTrig, clk_in, TS, TL, tempClk, and
reset. I'm clearly not connected this right.
Thanks for any input. Let me know if any other information is needed.
Ouch! There are multiple basic bugs in this description.
A port map is "port_signal => external_signal" from the view of the
Your tempclk is the external signal:
> signal tempclk : std_logic;
and your clk_24khz is the port signal:
> component pulse_counter is> port ( clk_24Khz : in std_logic;
So this assignment here (and as far as I see most of the others also) is
the wrong direction:
> U3 : pulse_counter port map (tempclk=>clk_24KHz, ...
> U1 : SeqLogic port map (V=> V_sensor,
You MUST(!!) pass eyery asynchronous external signal through at least
one better are two synchronisation flipflops before you use it inside
your design. See this here:
> mclk, tempclk, clk_24khz ...
Far way much too much clocks in this beginners design!!
A beginners design must have exactly 1 clock. All the rest is done by
clock enables. See there the very last code snippet:
The whole design has only clk as clock. 't' is the clock enable.