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Forum: FPGA, VHDL & Verilog Port Map Errors


Port Map Errors
von Jay J. (jboss10)

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I have quite a large project involving a Traffic Light system. I'm at 
the point of port mapping all of my blocks together within the top 
entity as I will post..

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library IEEE; 

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use ieee.std_LOGIC_1164.all; 

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entity Final_TLSystem is 

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port

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   (V_Sensor          :  in  std_logic;

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    mclk         :  in  std_logic; 

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    mst_reset       :  in  std_logic; 

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    Traffic_Lights   :  out std_logic_vector ( 5 downto 0)

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    ); 

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end Final_TLSystem; 

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  architecture Final_TLSystem_arch of Final_TLSystem is 

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  signal internal     : std_logic_vector (1 downto 0);

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  signal tempTrig : std_logic_vector (1 downto 0);

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  signal tempclk   : std_logic; 

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  signal tempTime : std_logic_vector (1 downto 0);

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  component SeqLogic is

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  port     (clk_in  : in  std_logic;

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         reset   : in  std_logic; 

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         TS      : in  STD_logic;

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         TL      : in  std_logic; 

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         V       : in  std_logic; 

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         S        : out std_logic_vector (1 downto 0)

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         );

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  end component; 

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component TLightSystem is 

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  port  (State_In : in  std_logic_vector  (1 downto 0);   

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        Lights   : out std_logic_vector (5 downto 0);

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       TS_TL   : out std_logic_vector (1 downto 0)

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       );

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end component;

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--component FreqDivider is

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  --  port(

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    --     clk_24MHz : in STD_LOGIC;

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     --    clk_24KHz : out STD_LOGIC

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     --    );

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--end component;

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component pulse_counter is

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port     ( clk_24Khz     : in  std_logic; 

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        trigger_long  : in  std_logic; 

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        trigger_short : in  std_logic; 

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        TS         : out std_logic; 

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        TL         : out std_logic 

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       );

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end component; 

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begin 

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  U1 : SeqLogic      port map (V=> V_sensor, internal(0)=>S(0), internal(1)=>S(1),tempTrig(0) => TS, tempTrig(1)=>TL, tempclk=>clk_in, reset=> mst_reset); 

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  U2 : TLightSystem  port map (Lights=>Traffic_Lights, tempTrig(0)=> TS_TL(0), tempTrig1=> TS_TL(1), tempS0=> State_In(0), tempS1 => State_In(1)); 

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  U3 : pulse_counter port map (tempclk=>clk_24KHz, tempTime(0)=> TS, tempTime(1)=>TL, tempTrig(0)=> trigger_long, tempTrig(1)=>trigger_short, clk_24KHz=>mclk);  

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end Final_TLSystem_arch;


Errors I'm receiving:
"type of formal parameter "internal" does not match type or value"
"object "S" is used but not declared"
"cannot associate formal port "internal" of mode "object" with an 
expression"

..same errors trickle down with tempTrig, clk_in, TS, TL, tempClk, and 
reset. I'm clearly not connected this right.

Thanks for any input. Let me know if any other information is needed.

  


  




  

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    Re: Port Map Errors
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Ouch! There are multiple basic bugs in this description.

First:
A port map is "port_signal => external_signal" from the view of the 
component.
Your tempclk is the external signal:
> signal tempclk   : std_logic;
and your clk_24khz is the port signal:
> component pulse_counter is
> port ( clk_24Khz  : in  std_logic;
So this assignment here (and as far as I see most of the others also) is 
the wrong direction:
> U3 : pulse_counter port map (tempclk=>clk_24KHz, ...

Second:
> U1 : SeqLogic      port map (V=> V_sensor,
You MUST(!!) pass eyery asynchronous external signal through at least 
one better are two synchronisation flipflops before you use it inside 
your design. See this here:
http://www.lothar-miller.de/s9y/archives/64-State-Machine-mit-asynchronem-Eingang.html


Third:
> mclk, tempclk, clk_24khz ...
Far way much too much clocks in this beginners design!!
A beginners design must have exactly 1 clock. All the rest is done by 
clock enables. See there the very last code snippet:
http://www.lothar-miller.de/s9y/archives/80-Hello-World!.html
The whole design has only clk as clock. 't' is the clock enable.

  


  




  

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    Re: Port Map Errors
  


  

    

      von
      
        asd (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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1
  U1 : SeqLogic      port map (V=> V_sensor, internal(0)=>S(0), internal(1)=>S(1),tempTrig(0) => TS, tempTrig(1)=>TL, tempclk=>clk_in, reset=> mst_reset); 

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  U2 : TLightSystem  port map (Lights=>Traffic_Lights, tempTrig(0)=> TS_TL(0), tempTrig1=> TS_TL(1), tempS0=> State_In(0), tempS1 => State_In(1)); 

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  U3 : pulse_counter port map (tempclk=>clk_24KHz, tempTime(0)=> TS, tempTime(1)=>TL, tempTrig(0)=> trigger_long, tempTrig(1)=>trigger_short, clk_24KHz=>mclk);


wrong order of port map assignments. Should be S(0)=>internal(0) for 
example...
Would also be much more readable with some line feeds:

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U1 : SeqLogic

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  port map (

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   V      => V_sensor,

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   S      => internal,

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   TS     => tempTrig(0),

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   TL     => tempTrig(1),

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   clk_in => tempclk,

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   reset  => mst_reset);

something in that style...

  


  




  

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