EmbDev.net

Forum: FPGA, VHDL & Verilog Seven Segment Display design with 2 4-1 MUXes


von Keith F. (Guest)


Rate this post
0 useful
not useful
I am a tad bit lost with going about how to code this. I was given 2 
types of code to help me with this design but I'm lost at coding the 2 
4-1 MUXes into the SSeg decoder. Any help is greatly appreciated!


Here is the provided coding I was given:
1
//Hex to SSeg LED decoder
2
module hex_to_sseg
3
   (
4
    input wire [3:0] hex,
5
    input wire dp,
6
    output reg [7:0] sseg  // output active low
7
   );
8
9
   always @*
10
   begin
11
      case(hex)
12
         4'h0: sseg[6:0] = 7'b0000001;
13
         4'h1: sseg[6:0] = 7'b1001111;
14
         4'h2: sseg[6:0] = 7'b0010010;
15
         4'h3: sseg[6:0] = 7'b0000110;
16
         4'h4: sseg[6:0] = 7'b1001100;
17
         4'h5: sseg[6:0] = 7'b0100100;
18
         4'h6: sseg[6:0] = 7'b0100000;
19
         4'h7: sseg[6:0] = 7'b0001111;
20
         4'h8: sseg[6:0] = 7'b0000000;
21
         4'h9: sseg[6:0] = 7'b0000100;
22
         4'ha: sseg[6:0] = 7'b0001000;
23
         4'hb: sseg[6:0] = 7'b1100000;
24
         4'hc: sseg[6:0] = 7'b0110001;
25
         4'hd: sseg[6:0] = 7'b1000010;
26
         4'he: sseg[6:0] = 7'b0110000;
27
         default: sseg[6:0] = 7'b0111000;  //4'hf
28
     endcase
29
     sseg[7] = dp;
30
   end
31
32
endmodule
33
34
//4-1 Mux
35
module mux( select, d, q );
36
37
input[1:0] select;
38
input[3:0] d;
39
output q;
40
41
reg q;
42
wire[1:0] select;
43
wire[3:0] d;
44
45
always @( select or d )
46
begin
47
   if( select == 0)
48
      q = d[0];
49
50
   if( select == 1)
51
      q = d[1];
52
53
   if( select == 2)
54
      q = d[2];
55
56
   if( select == 3)
57
      q = d[3];
58
end
59
60
endmodule

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
Keith F. wrote:
> Here is the provided coding I was given:
And what did you do yourself already? No one here is intended do do 
all of your homework...

> but I'm lost at coding the 2 4-1 MUXes into the SSeg decoder. Any help
> is greatly appreciated!
Thats the way it works: show your try and tell clearly whats the problem 
with it.

At least you musthave a sketch (on a piece of paper) how you would 
conntect those parts given. Then you can easily recognize, whats 
/missing/: you lack a counter steadily walking thru these 4 segments...

If you don't know it already: this here is obviously the 
Nibble-To-Segment decoder:
1
                  segments:   abcdefg
2
         4'h0: sseg[6:0] = 7'b0000001; // 0
3
         4'h1: sseg[6:0] = 7'b1001111; // 1
4
         4'h2: sseg[6:0] = 7'b0010010; // ....
5
         4'h3: sseg[6:0] = 7'b0000110;
6
         4'h4: sseg[6:0] = 7'b1001100;
7
         4'h5: sseg[6:0] = 7'b0100100;
8
         4'h6: sseg[6:0] = 7'b0100000;
9
         4'h7: sseg[6:0] = 7'b0001111;
10
         4'h8: sseg[6:0] = 7'b0000000;
11
         4'h9: sseg[6:0] = 7'b0000100; // 9
12
         4'ha: sseg[6:0] = 7'b0001000; // A
13
         4'hb: sseg[6:0] = 7'b1100000; // b
14
         4'hc: sseg[6:0] = 7'b0110001; // C
15
         4'hd: sseg[6:0] = 7'b1000010; // d
16
         4'he: sseg[6:0] = 7'b0110000; // E
17
         default: sseg[6:0] = 7'b0111000;  // F
And with the other code snippet you can obviously select one value out 
of 4, so that leads to the assumption, that you have 4 digits to 
display...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.