Hi guys,

I'm writing A VHDL code to interface a 16-bit serial ADC to an FPGA and 
I have some questions about my methodology. The ADC that I'm using is 
the AD7655 from analog device.

I think the code should be very simple, but I just want to get a second 
opinion so I don't end up in the wrong direction.
In fact, I'm not sure if I'm asserting and reading the data correctly. 
Anyway, this is methodology:

1. Since the ADC is going to be operating in External Clock Data Read 
(Previous) During Convert mode(page 22 of 
http://www.analog.com/static/imported-files/data_sheets/AD7655.pdf, my 
input clock needs to be 32 MHz at least. This is going to be fed into 
the ADC at all time. For this reason. I followed the detailed timing in 
Figure 33 in the datasheet to write my VHDL code.

2. Make a simple state machine with five state cases,ADC_STATE IS 
(IDLE,START,CONV_A,CONV_B,CATCH);

3. CONV will be asserted 1 in IDLE State, the CONV is asserted 0 in 
START state.

4. At the rising edge when the state is START, I make a test of BUSY 
signal, if it's high the  CONV_A state can start, in which the channel A 
is converted and date grabbed and placed into the register. I will stop 
at CLK = 16, and at CLK = 16, the  CONV_B state can be started.

5. in CONV_B state, the channel B is converted and date grabbed and 
placed into the register. I will stop at CLK = 16, and at CLK = 16, the 
CATCH state can be started.

6. In the CATCH state, I will put conversion values of channel A and 
channel B into another registers. Everything will now repeat by putting 
the state to IDLE one.

I am in the right direction? it my first experience to write code from a 
timing diagram.

In case you're interested, my code can be attached.

I'd appreciate any input you have for modification to get this thing 
going.

Best regards